Stun device testing apparatus and methods

ABSTRACT

A testing apparatus includes a housing having a port for receiving a discharge end of an electrical discharge device. A discharge-receiving circuit is operatively connected to the port, and is configured to receive a discharge from the electrical discharge device. The discharge-receiving circuit includes a default resistor and at least one supplemental resistor. When in a first setting, the discharge-receiving circuit is configured so as to pass the discharge automatically through at least the default resistor. When in a second setting, the discharge-receiving circuit is configurable so as to selectively pass the discharge through at least one of the plurality of resistors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of U.S. ProvisionalPatent Application Ser. No. 61/707,101, entitled “Stun Device TestingApparatus and Methods,” filed Sep. 28, 2012, the disclosure of which ishereby incorporated by reference herein in its entirety.

INTRODUCTION

The use of neuromuscular incapacitation (NMI) devices (and other stundevices that emit electrical discharges against a target mammal) hasincreased over the last decade to encompass over 200,000 units inoperation worldwide with over 800,000 actual firing deploymentsinvolving training personnel and law enforcement incidents. The outputof stun devices is electrical in nature and thus may not leave anidentifying mark or clear trace of historical events, unlike a bullet,that normally leaves such a mark. Furthermore, stun devices are designedto incapacitate effectively and temporarily an individual based on aunique and specific electrical output, as stated by a manufacturer.

Currently, there are many stun devices available around the world,featuring a variety of outputs with respect to voltage, current,waveform, and timing intervals. While many are available, however, onlya limited number of manufacturers sell stun devices in a gunform-factor. U.S. Pat. Nos. 7,234,262 and 6,636,412 by TaserInternational and U.S. Pat. No. 6,575,073 by Stinger Systems alldescribe currently available commercial stun devices. The disclosures ofthese patents are hereby incorporated by reference herein in theirentireties. The electrical output of each company's device differssignificantly from the others and within each specified output for agiven load, but each manufacturer makes their own claims ofeffectiveness and safety, as discussed below. The differences andcharacteristics of electrical output of stun devices are known fromdetailed and sophisticated measurements with a variety of specializedoscilloscopes and related measuring tools.

FIGS. 1, 1A and 2 and TABLE 1 show detailed traces of waveforms underspecific conditions using sophisticated oscilloscopes as well as asummary of typical electrical output for a variety of related,electrically-focused technologies used in the medical profession andother fields. FIG. 1 shows waveforms from a commercially available stundevice of a hand-held type, illustrating several important features ofthe waveform, including pulse height and charge, repetition rate, slopeof the peak, duration of the waveform, changing shape of the waveformand total energy delivered. FIG. 1 depicts the waveforms at fourresistances, while FIG. 1A depicts the waveforms of another stun device,at three resistances. FIG. 2 shows additional details of an “idealized”waveform discharged by a device presently in commercial use, indicatinga variety of characteristics. The characteristics shown in FIGS. 1, 1A,and 2 define the waveform of choice for a given device and manufacturer.TABLE 1 provides a comparison of stun devices, and includes similarinformation for biomedical devices employing electrical current, such asElectroconvulsive (ECT) therapy, cauterizing devices (electro-surgery),and defibrillators.

TABLE 1 Electrical Discharge Comparison of Various Device Types VoltageCurrent Pulse Duration Pulse Frequency Power Electric Fencing 5-10 kV10-20 mA 0.1-1 sec 0.5-1 Hz   0.1-18 J/pulse  Early Stun Devices 40-100kV 3-4 mA ~20 μsec  5-20 Hz 0.8 J/pulse 7 watt Taser Current StunDevices 18-50 kV  2-4 mA average   11 μsec 10-25 Hz 0.1-1.8 J/pulse 26watt Taser 18 A peak ECS, ECT  70-450 V 20-900 mA 1.5 msec      70 Hz0.6 J/pulse Defibrillators  ~750-1500 V   20-65 A 5-7 msec 1-6 total100-360 J/pulse Electrosurgery 1000-9000 V variable variable <200,000 Hz80-300 Watts

It is helpful to note that a manufacturer's claim of effectiveness andsafety must be linked directly to a consistent electrical output.Manufacturers have conducted various safety studies involving humans andanimals to allay public fears and to use as a defense in litigation,where the actual output of the device is considered to have been a causeof injury or death of the target. Thus, lacking regulatory approval of auniversal waveform, each company documents its waveform's safety byperforming safety studies for its own devices. While safety factors ofeach waveform have been disclosed in publications, the device use dataand associated instances of injury and death to date also revealssignificant questions regarding safety. Thus, the identity and integrityof a specific waveform is of high value to a number of stakeholdersincluding manufacturers, end-users (e.g., law enforcement) and thepublic on whom the devices are deployed for non-lethal purposes.Examples of studies resulting in claims of both safety and potentialinjury can be found, for example, in the following publications: JeffreyD. Ho, MD, James R. Miner, MD, Dhanunjaya R. Lakireddy, MD, Laura L.Bultman, MD, William G. Heegaard, MD, MPH, “Cardiovascular andPhysiologic Effects of Conducted Electrical Weapon Discharge in RestingAdults,” ACADEMIC EMERGENCY MEDICINE, 13:589-595 (2006); Valentino, D.J., Walter, R. J., Dennis, A. J., Nagy, K., Loor, M. M., & Winners, J.et al., “Neuromuscular effects of stun device discharges,” JOURNAL OFSURGICAL RESEARCH, 143(1), 78-87 (2007); Valentino, D. J., Walter, R.J., Nagy, K., Dennis, A. J., Winners, J., & Bokhari, F. et al.,“Repeated thoracic discharges from a stun device,” JOURNAL OFTRAUMA—INJURY, INFECTION AND CRITICAL CARE, 62(5), 1134-1142 (2007); A.Esquivel, E. Dawe, J. Sala-Mercado, R. Hammond, C. Bir, “The PhysiologicEffects of a Conducted Electrical Weapon in Swine,” ANNALS OF EMERGENCYMEDICINE, Vol. 50, Issue 5, Pages 576-583 (2007); Lakkireddy, D.,Khasnis, A., Antenacci, J., Ryshcon, K Chung, M. K., & Wallick, D. etal., “Do electrical stun guns (TASER-X26®) affect the functionalintegrity of implantable pacemakers and defibrillators?,” EUROPACE,9(7), 551-556 (2007); and Lakkireddy, D., Wallick, D., Ryschon, K Chung,M. K Butany, J., & Martin, D. et al., “Effects of cocaine intoxicationon the threshold for stun gun induction of ventricular fibrillation,”JOURNAL OF THE AMERICAN COLLEGE OF CARDIOLOGY, 48(4), 805-811 (2006).The disclosures of these references are hereby incorporated by referenceherein in their entireties.

Notwithstanding a manufacturer's claim of safety, electric stun devicesafety can only be assured if the stated waveform is both proven safeand is consistently produced and delivered by the device. Given theimportance of this link between device output, safety, andeffectiveness, we have determined it to be desirable that the output beverifiable for a given device during its cycle of normal duty and on aschedule of appropriate timing to ensure that only devices havingoutputs that are studied and verified safe are used on targets. However,there is no easy, simple way to verify device output on a regular basiswithin the typical law enforcement context. Thus, we have determinedthat verification of device output is needed in the law enforcementsetting, in a testing apparatus that is simple to operate andinexpensive to purchase.

It also is reasonable to assume that as stun devices of differentmanufacturers and types become even more widely deployed and betterstudied, there will be a need to examine in detail the output of aspecific device or class of devices. This output may be in relation to aspecific incident or a class of incidents in which one or more devicesare involved, including devices by different manufacturers. In such acase, currently, it is necessary to use sophisticated oscilloscopesoperated by an expert or someone very familiar with the measurementequipment and the particular features of stun devices to capture, studyand analyze the device's electrical output. Further, the waveform mustbe interpreted to assess whether it is, in fact, safe. While thisapproach may be helpful in determining the safety of a device right offthe assembly line, stun devices are rarely, if ever, tested after beingin the field for a period of time. Moreover, any tests performed on aparticular device are often performed only after a discharge against atarget has occurred, usually, and unfortunately, after there exists areason for testing (e.g., an unintentional death of a target duringdeployment). There is essentially no focus on the actual routineverification of output prior to routine use. In addition, becauseelectrical currents are transient and may not leave tangible traces thatare currently recognized by the medical profession, the commonlyrecognized characteristics of an electrical discharge (voltage,amplitude, etc.) are often the only measure of output that was receivedby the target. These commonly recognized characteristics may not besufficient, in all circumstances, to determine adequately or reliablythe reason for an adverse result (i.e., a death of a target).

Moreover, if one follows the analogy of forensic study of ballisticevidence, it is clear that the capability to collect and analyzeelectric stun discharge evidence is lacking. Thus, we have determinedthat it is highly advantageous to have a device or series of measurementdevices that are easy to operate and understand and are linked to theknown waveform output of stun devices available. While some attempts arebeing made to develop systems to test particular stun devices from aspecific manufacturer, these attempts do not appear to contemplate adevice that test both existing and not-yet-developed stun devices, or totest and compile information on both existing and not-yet-developed stundevices to enable research into the safety and efficacy of electricwaveforms and stun devices, generally. See, e.g., Nelson Bennett,“lasers' test results sparks technology,” Richmond News (Sep. 9, 2009)(available athttp://www2.canada.com/richmondnews/news/story.html?id=0fa3b787-b632-4543-a991-354de3f9cd74),the disclosure of which is hereby incorporated by reference herein inits entirety.

Additionally, having these devices readily available (both economicallyand physically) would allow law enforcement departments and forensicinvestigators and coroners the capability of in-depth analysis of stundevice discharges, as needed.

Stun device output is a function, in part, of the internal electroniccircuitry designed to produce a given waveform of a given magnitude andduration. We have determined that it would be desirable for thedischarge output to be verified during the life cycle of a device.Changes in output can occur due to a number of factors, including, butnot limited to, defective manufacture, component failure due to use,current leakage to operator, change in manufacturing components,deliberate alteration of components and power supply, etc. Additionally,manufacturers develop and sell successor models of stun devices (e.g.,Taser models M18, M26, X26, wireless systems, sentry systems; seewww.taser.com) and may alter the original waveform and output as modelschange over time. Moreover, nearly all projectile-based gun-platformstun devices may also deliver a subcutaneous electrical dischargesignificantly different than a discharge directly against the skin.Thus, manufacturers' stated claims of output should not be relied uponas accurate over the lifetime of use of the device, nor across successormodels. It would be desirable to verify such output on a routine basis.

Currently, stun device output is not regulated at the state or federallevel with respect to waveform or magnitude, nor are manufacturingstandards tied to any stated degree of device performance or acceptabledeviation from stated specifications. Without verification, there islittle, if any, accountability for holding manufacturers responsible forquality performance features. The lack of verification is problematicfor law enforcement officials who use the devices routinely and who maybe involved in litigation due to a specific, often fatal, incident. Suchdetails become important in complex deployment situations where drugs,alcohol and extreme agitation, as well as a victim's pre-existingconditions (such as use of pacemakers, etc.) are present. Medicalexperience has shown that risks from electrical stimulation includeabnormal heart rhythms, epileptic seizures, cell injury and death. Whilethere is an extensive history of the use of stun-devices with noapparent long term effects, the possibility exists. Variations from thenormal stimuli are of particular concern. For example very fast,high-amplitude transients can produce injury inside of cells.Ventricular fibrillation can be induced more easily at some rates, aswell. Thus, a convenient and cost effective program by law enforcementto track and record the features of the devices deployed over time maybe desirable.

Currently, a number of oscilloscopes and other measuring devices areemployed for the detailed analysis of waveforms and output of stundevices. Many of these measuring devices and oscilloscopes aresophisticated with respect to data capture rate, range and magnitude ofsignal, signal sampling parameters, and ability to analyze, record andhandle large amounts of stored data. The technology involved in typicalelectrical output analysis includes a multimeter as described in U.S.Pat. No. 7,342,393, issued Mar. 11, 2008, to Newcombe; combination testinstruments and voltage detectors as described in U.S. Pat. No.7,242,173, issued Jul. 10, 2007, to Cavoretto; devices generatingelectronic test signals as described in U.S. Pat. No. 6,944,569, issuedSep. 13, 2005, to Harbord; digital oscilloscopes with waveform patternrecognition as described in U.S. Pat. No. 6,621,913, issued Sep. 16,2003, to de Vries; specialized circuits for measuring in-circuitresistance and current as described in U.S. Pat. No. 5,804,979, issuedSep. 8, 1998, to Lund; and devices designed to detect minimum pulsewidths of waveforms as described in U.S. Pat. No. 5,708,375, issued Jan.13, 1998, to Lemmens. U.S. Pat. No. 6,469,492, issued Oct. 22, 2002, toBritz and U.S. Pat. No. 5,930,745, issued Jul. 27, 1999, to Swiftdisclose additional testing equipment. The disclosures of each of theabove-identified references are incorporated by reference herein intheir entireties.

Additionally, there are a number of devices that are used to measure andverify electrical signals from a variety of biomedical devices includingdefibrillators, as described in U.S. Published Patent Application No.2007/0226574, published Sep. 27, 2007, by Ryan; pacemakers, as describedin U.S. Pat. No. 5,209,228, issued May 11, 1993, to Cano;electro-surgery devices; and others. Many electrical testing devicesprovide comparisons with known electrical standards such as theInternational Electrotechnical Commission (IEC) and the Association forthe Advancement of Medical Instrumentation (AAMI). The disclosures ofeach of the above-identified references are incorporated by referenceherein in their entireties.

However, no universal test devices currently exist that can consistentlymeet the needs described above for known and to-be-developed stundevices. Additionally, there presently exists no method for imposingaccountability on users or manufacturers of stun devices by proving howa particular stun device was operating prior to discharge during routineuse against a target. Moreover, there exists no system for collectinginformation and storing it reliably for “large data” analysis about stundevice discharge characteristics to study the effects of stun devices onan industry-wide basis.

SUMMARY

The technology disclosed herein consists of one or more testing devicesor apparatus that are capable of a spectrum of measurements anddata-handling features. The testing devices according to the technologyinclude an adapter for effective, consistent, and safe coupling to aninstrument capable of accepting, recording and analyzing the outputs ofa stun device. Some of the contemplated testing devices includeinterchangeable adapters specific to testing particular stun devices.The testing device, in a basic form, may record only total electricaloutput, maximum voltage and current, or other simple numerical data. Amore complex embodiment can also allow capture of waveformcharacteristics such as frequency, repetition rate, pulse trainduration, anomalies, etc., at several different load options, eachsimulating contact with the human body. Other embodiments can provideoptions of waveform analysis, as compared to a “standard” waveformsupplied by a manufacturer or other source. Embodiments of other devicescan be equipped with data storage and analytical features, libraries ofwaveforms of various devices, statistical programs, and a variety ofresistance factors simulating electrical pathways through human tissue.Other testing devices according to the technology can also be used torecord total output and waveform features for repeated applications ofstun devices. Furthermore, certain of these testing devices can reportoutput relative to existing or new standards, regulations, andprotocols, for the stun device industry as they are developed, relativeto a variety of electrical safety standards in the U.S. or otherjurisdictions, or relative to a set of specific standards for stundevices. These standards, regulations, or protocols may be developed bystun device manufacturers, governments, industry organizations,non-governmental organizations, medical organizations, standards-settingorganizations, etc.

One difference between the technical features of many of the testingdevices described in the Background and one embodiment of the stundevice safety tester as described below, is the basic unit of electricalsampling. Available stun devices produce pulses with durations rangingfrom less than 1 microsecond to tens of milliseconds. In addition,transients associated with spark-gap type stun devices have durationsthat are fractions of a microsecond, as shown in FIG. 3 (note, e.g.,leading spike on negative lobe). Thus, in contrast to defibrillatortesters that measure single and very large pulses and pacemakeranalyzers that measure relatively wide (slow) pulses over a very shortperiod, the stun device tester in one embodiment will record thedetailed behavior of waveforms with features ranging from very fast,high magnitude transients to normal pulse durations of tens ofmilliseconds. This suggests sampling rates of at least 20 megasamples/second for 10 milliseconds, demanding 200,000 words of storageto recreate waveforms or 20,000 words of storage to identify thepresence of fast transients. Sampling rates of 10 mega samples/secondmay also be utilized. In one embodiment, normal waveforms from aspectrum of devices can be captured and analyzed as well as chaotic andvery fast anomalies that, to date, have not been characterized for stundevices. While the medical and safety significance of such transientsand anomalies are not entirely understood, such aberrations can beidentified and measured to assess their relevance and to help ensureclaimed output parameters and safety.

In one aspect, the technology relates to an apparatus including: ahousing including a port for receiving a discharge end of an electricaldischarge device; and an discharge-receiving circuit operativelyconnected to the port, the discharge-receiving circuit configured toreceive a discharge from the electrical discharge device, wherein thedischarge-receiving circuit has: a plurality of resistors including adefault resistor and at least one supplemental resistor, wherein when ina first setting, the discharge-receiving circuit is configured so as topass the discharge automatically through at least the default resistor,and wherein when in a second setting, the discharge-receiving circuit isconfigurable so as to selectively pass the discharge through at leastone of the plurality of resistors. In an embodiment, the at least onesupplemental resistor includes a first supplemental resistor and asecond supplemental resistor. In another embodiment, a resistance of thedefault resistor is higher than a resistance of at least one of thefirst supplemental resistor and the second supplemental resistor. In yetanother embodiment, the apparatus includes a switch for selectivelysetting the discharge-receiving circuit to either of the first settingand the second setting. In still another embodiment, thedischarge-receiving circuit is set to the first setting when thedischarge-receiving circuit is unpowered.

In another embodiment of the above aspect, the apparatus includes anenvironmental module for detecting at least one of an ambienttemperature, an ambient humidity, and a barometric pressure. In anotherembodiment, the apparatus includes an air intake fan for drawing ambientair into the housing, and wherein the environmental module detects atleast one of the ambient temperature and the ambient humidity, andwherein the environmental module is disposed downstream of the airintake fan. In another embodiment, the discharge-receiving circuitfurther includes an analysis module.

In another aspect, the technology relates to a method of configuring acircuit, the method including: detecting a condition indicative of aloss of power to the circuit; configuring the circuit such that anelectrical discharge through the circuit is routed through at least oneof a plurality of resistors, wherein the electrical discharge isreceived from a device located external to the circuit. In anembodiment, the method includes receiving the electrical discharge fromthe external device. In another embodiment, the method includesdetecting a condition indicative of a receipt of power to the circuit;and selectively configuring the circuit so as to route the dischargethrough at least one of the plurality of resistors. In yet anotherembodiment, the method includes selecting a protocol; and selectivelyconfiguring the circuit based at least in part on the selected protocol.In still another embodiment, the condition is based at least in part onthe position of a switch in the circuit.

In another embodiment of the above aspect, the condition is based atleast in part on an absence of supply power to the circuit. In anotherembodiment, configuring the circuit has at least one of opening orclosing a solenoid. In another embodiment, the circuit is disposedwithin a testing device.

In another aspect, the invention includes an article of manufacturehaving a computer-readable medium with computer-readable instructionsembodied thereon for performing the methods described in the precedingparagraphs. In particular, the functionality of a method of the presentinvention may be embedded on a computer-readable medium, such as, butnot limited to, a floppy disk, a hard disk, an optical disk, a magnetictape, a PROM, an EPROM, CD-ROM, DVD-ROM or downloaded from a server. Thefunctionality of the techniques may be embedded on the computer-readablemedium in any number of computer-readable instructions, or languagessuch as, for example, FORTRAN, PASCAL, C, C++, Java, PERL, LISP,JavaScript, C#, Tel, BASIC and assembly language. Further, thecomputer-readable instructions may, for example, be written in a script,macro, or functionally embedded in commercially available software (suchas EXCEL or VISUAL BASIC).

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the present technology, as well as thetechnology itself, can be more fully understood from the followingdescription of the various embodiments, when read together with theaccompanying drawings, in which:

FIG. 1 depicts a graph of waveforms from a commercially-available stundevice, under four different resistor loads.

FIG. 1A depicts a graph of waveforms from another commercially-availablestun device, under three different resistor loads

FIG. 2 depicts waveform detail and characteristics of a commerciallyavailable stun device.

FIG. 3 depicts waveform detail of a particular waveform produced by thestun device of FIG. 2.

FIG. 4A depicts a schematic perspective view of a stun device testingsystem in accordance with an embodiment of the technology.

FIG. 4B depicts a schematic perspective view of a stun device testingsystem in accordance with another embodiment of the technology.

FIG. 5A depicts a schematic block diagram of a stun device testingsystem in accordance with another embodiment of the technology.

FIG. 5B depicts a schematic block diagram of a stun device testingsystem in accordance with another embodiment of the technology.

FIG. 6A depicts a schematic diagram of a stun device testing system inaccordance with another embodiment of the technology.

FIG. 6B depicts a schematic cross-sectional side view of an interfacefor a stun device testing system in accordance with one embodiment ofthe technology.

FIG. 6C depicts a partial perspective view of an interior portion of ahousing for a stun device testing system in accordance with oneembodiment of the technology.

FIG. 7A is a schematic block diagram of a hardware configuration of astun device testing system in accordance with an embodiment of thetechnology.

FIG. 7B is a schematic block diagram of a field programmable gate arrayconfiguration for a stun device testing apparatus in accordance with anembodiment of the technology.

FIG. 8A is a schematic block diagram of a hardware configuration of astun device testing apparatus in accordance with another embodiment ofthe technology.

FIG. 8B is a schematic block diagram of function performed by thehardware configuration of FIG. 8A.

FIG. 9A is a schematic diagram of a circuit utilized in the hardwareconfiguration of FIG. 7A.

FIG. 9B is a schematic diagram of a circuit utilized in a stun devicetesting system in accordance with another embodiment of the technology.

FIGS. 10A-10C depict a block diagram of a hardware configuration of astun device testing apparatus in accordance with another embodiment ofthe technology.

FIGS. 11-11F depict a schematic diagram of a front end circuit utilizedin the hardware configuration of FIGS. 10A-10C.

FIGS. 12-121 depict a schematic diagram of control circuit utilized inthe hardware configuration of FIGS. 10A-10C.

FIGS. 13-13D depict a schematic diagram of a power circuit utilized inthe hardware configuration of FIGS. 10A-10C.

FIGS. 14-14H depict a schematic diagram of a sensor circuit utilized inthe hardware configuration of FIGS. 10A-10C.

FIGS. 15A-15B depict an example CPLD clock diagram in accordance withone embodiment of the technology.

FIGS. 16A-16C depict an example addressing scheme in accordance with oneembodiment of the technology.

FIGS. 17A-17B depict output load responses to output load steps.

FIG. 17C depict a frequency and phase plot of a response of an inputcircuit.

FIG. 17D depicts an output load response to an output load step.

FIGS. 18A-18C depict waveform details and characteristics of the stundevice of FIG. 2.

FIG. 19 depicts a method of testing an electric discharge stun device,in accordance with one embodiment of the technology.

FIG. 20 depicts a method of ensuring proper operation of an electricdischarge stun device, in accordance with one embodiment of thetechnology.

FIG. 21 depicts a method of determining a biological response to anelectric discharge from a stun device, in accordance with one embodimentof the technology.

FIG. 22 depicts a method of configuring a circuit in a stun devicetesting system in accordance with another embodiment of the presenttechnology.

DETAILED DESCRIPTION

FIG. 4A depicts a schematic perspective view of a stun device testingand data storage system 100 in accordance with an embodiment of thetechnology. The system 100 may include a tester 102, a computer 104 ofany type (desk top, hand-held, PDA, laptop, etc.), a printer 106, and,optionally, an ethernet or other connection 108 to an external network110. The various components of the system 100 may be connected via cableconnections 112 or a wireless connection (not shown) of any type. Thedepicted system is able to record and store captured data for analysisof waveforms. Such analysis may be supported by extensive libraries ofwaveforms and other analytical tools, such as single or multiplesoftware programs for the specific purpose of analysis, as appropriate,to maintain, manage and/or verify outputs of stun devices. Moreover,reporting of data via secure data custody links can be integrated instate and federal databases for the effective tracking of deviceperformance and safety compliance. These libraries may be maintainedeither within the tester 102, the computer 104, or in an externaldatabase, accessed via the network 110. The libraries of information maybe accessed or updated on a regular or semi-regular basis by softwareutilized by the computer 104 or the tester 102. Additionally, theinformation obtained from the system 100 may be sent via the network 110to an electronic information repository (e.g., the cloud) that stores,processes, analyzes, etc., information from any number of similarsystems, thus quickly building a database of information to be used andaccessed by all authorized users of the systems. Authorized researcherscould also access the data repository to perform additional research andanalysis.

In one embodiment of the technology, the data from each discharge may bestored in a first storage medium, remote from or local to the device.All other information (e.g., historical data from previously testeddevices, known data from known stun devices or manufacturers, etc.) maybe stored in a second storage medium. In this way, the information inthe second medium may be updated on a regular or semi-regular basis (asdescribed in further detail herein), while the information in the firstmedium serves as a record for all tests performed with the testingsystem. In certain embodiments, the first and second mediums may be asingle medium for information storage. In certain embodiments, the datamay be stored in a compressed format, for example, compressed to afactor of up to about 10:1. Other compression factors may be utilized.

In the system 100 depicted in FIG. 4A, the tester 102 includes a shallowhousing 120 that may be mounted on a wall at shoulder height.Alternative embodiments may be configured for table-top usage, or may bedimensioned to be portable. Such portable devices may be maintained in acarrying case and may include power, communication or other cablingrequired to use the tester in remote locations. The front of the boxpresents four testing ports 122 (labeled 1, 2, 3 and 4) and twoidentification ports 124, 126. The operation and configurations of thetesting ports 122 are described below. In some embodiments, describedbelow, a single port may be utilized to perform the measurementsdescribed herein, with the stun device tester automatically adjustingthe resistance values and/or spark gap configurations during a stundevice testing procedure. A single port may be particularly desirable incertain embodiments because it reduces potential shock hazards. In otherembodiments, two ports utilizing spark gaps and two ports without sparkgaps may be used (adjusting the resistance values as required during astun device testing procedure). Still other embodiments may utilize twolow resistance ports and two high resistance ports (adjusting the sparkgap as required during a stun device testing procedure).

In the tester 102 depicted in FIG. 4A, the four testing ports areutilized to determine a terminal model of the stun device under test.Both the voltage and current developed by a stun device may be used todetermine the terminal model. Voltage V is fairly straightforward tomeasure directly. Current I is usually measured by observing the voltagedeveloped across a known resistance R (or impedance), and derived usingthe formula I=V/R. Thus, to determine the current, R must be known. Todetermine the nature of the voltage source, total resistance needs to beknown. The total actual resistance is the sum of the resistance of thesource and the resistance of the load. The resistance of the load may beestimated by analysis or statistical measurement. In general, it hasbeen determined that, for a stun device tester, a load resistance in therange of about 30 ohms to about 300 ohms is desirable. To predict thecurrent developed by the stun device, the source resistance must also bedetermined. This can be done by measuring the voltage developed acrosstwo different, known load resistances. In one example, a firstmeasurement is conducted with a 50 ohm load, which is associated with afirst testing port 122 (port 1, for example) on the tester 102. A secondmeasurement is conducted with a 100 ohm load, which is associated with asecond testing port 122 (port 2, for example) on the tester 102. In thefirst measurement, 5000 volts is developed across 50 ohms; in the secondmeasurement 6667 volts is developed across 100 ohms. The equationsgoverning the two measurements may be simultaneously solved to determinethat the source voltage is 10000 and the source resistance is 50 ohms.Thus, the two measurements (i.e., two experiments) yield two values thatcan be used to determine the source resistance.

The other two ports 122 (ports 3 and 4, for example) utilize a spark gapin series with the load resistance. Port 3, for example, utilizes aspark gap across 50 ohms; and port 4, for example, utilizes a spark gapacross 100 ohms. Spark gaps generally have a very low resistance whenconducting, accordingly, there is little appreciable increase in theload resistance. However, spark gaps may introduce transients in thestun device discharge that may affect the stimulus from the device in apotentially injurious way to a target. The behavior of spark gaps isdependent, in part, on the amount of current conducted by the spark gap.Accordingly, two of the ports repeat the measurements with two differentload resistances, but also utilize the spark gaps to allow observationof their effect, if any. Spark gaps are present in certain stun devices.

The first identification port 124 may be utilized to read RFID tags oneither or both of a stun device and a badge or other uniqueidentification associated with a user. Alternatively, other readers (forexample, bar code readers or other optical or tactile scanners) may beutilized. The second identification port 126 may also or alternativelybe utilized to identify a user based on a biometric identifier, such asa user fingerprint. Other biometric systems (for example, voicedetectors, retinal scanners, etc.) also may be utilized. A source ofillumination may be associated with any or all of the elements and canbe used to guide the user through the testing steps. The source ofillumination may be a light bulb or light-emitting diode (LED) locatedwithin or proximate each port, for example.

The tester 102 can be used for purposes of registration and devicecharacterization. In one embodiment of a test sequence, a user starts astun device test by placing a finger in the fingerprint reader 126. Thetester 102 responds by illuminating the fingerprint reader light.Additionally, the computer 104 may be activated to provide additionalprompts to the user, or to record the testing sequence and results.Regardless, if the user is registered to use the system 100 and/or astun device, the fingerprint reader light turns off and the lightassociated with the RFID reader 124 is illuminated. The user thenpositions the stun device by the reader 124. Successful reading of aregistered stun device results in the illumination of testing port 1.The user places the stun device in testing port 1 and discharges thedevice. Successful reading results in turning off the light in testingport 1 and turning on the light in testing port 2. This processcontinues until the stun device has been successfully discharged at allfour ports. The tester uses the associated computer 104 to archive thedischarge data in the central repository (alternatively, the computer104 may archive the data automatically, either at that time, or later)and, if desired, prints out a summary of the test results on anassociated printer 106. The summary may include the measured averageenergy duration of each stimulus pulse, the number of pulses and totalduration of the stimulus, an estimate of the battery condition based onthe stun device's previous archived test results, changes observedwithin the current test, etc. Additionally, it may report the number andnature of observed variations from normal discharge. Advisoryinformation including “Replace Battery” and “DO NOT USE” may also beincluded in the report. Additionally, the summary may include an imageof the waveform, and/or other relevant characteristics thereof. Thesummary may also include an indication of whether the stun device isapproved for subsequent use on a target, based on an analysis of thewaveform or other discharge characteristic. The printed summary also mayserve an important documentary function, creating a record of theoperation of the device prior to use against a human target.

FIG. 4B depicts a schematic perspective view of a stun device testingsystem 150 in accordance with another embodiment of the technology. Thesystem 150 includes a tester 152 that may communicate, via a wirelessnetwork 154, with a computer 156 and/or a remote storage database 158.Wireless communication helps reduce or eliminate the likelihood ofundesirable electrical events being directed to, e.g., the computer 156,should an error occur at the tester 152 when receiving a discharge froma stun device. As described above, the tester 152 also may be astand-alone device that performs all processes described herein. In thedepicted embodiment, the tester 152 includes a single port 160 on ahousing 162 for receipt of a discharge end of a stun device. The tester152 also includes a user interface 164, in this case, a touch screenthat displays a graphic user interface. A cord 166 connects the tester152 to a source of power, such as a building power source, auxiliaryvehicle power source, or other source. Alternatively or additionally,the tester 152 may include a switch 168 used to toggle power to thetester 1523. As described below, the tester 152 may be configured suchthat an unpowered tester 152 may still receive discharges safely, evenwhen unplugged or powered off.

The computer 156 and/or remote storage database 158 may connect to thewireless network 154 so as to communicate with the tester 152. In otherembodiments, the tester 152 may communicate directly with the computer156 and/or remote storage database 158 via a Bluetooth, RFID, or otherwireless or wired connection. In an alternative embodiment, the tester152 may be controlled by the remote computer 156, which may displayon-screen instructions typically displayed on the display 164 of thetester 152. The internal configuration of the tester 152 is described infurther detail below. The tester 152 is utilized to test stun devicesthat have both a high discharge voltage and frequency, thus layout ofthe internal circuits, as well as automation of the testing processeshelps ensure consistent results.

FIG. 5A is another embodiment of a stun device testing and data storagesystem 200. The system 200 includes a tester 202 having one or moretesting ports or interfaces 222 for receiving a discharge end of a stundevice SD. The tester 202 also includes a processor 230 for processingthe data received from the stun device SD discharge, as well as forcontrolling the various elements of the tester 202, described below. Theprocessor 230 receives information from a sensing circuit 232, whichreceives the discharge from the stun device SD. The processor 230 alsocommunicates with the user interface 234, which may include one or morediscrete components. One component may be a first identification port224, as described above, i.e., a bar code scanner, RFID reader, etc.Other elements of the user interface 234 include a second identificationport 226 (e.g., a fingerprint scanner, a voice recognition device, aretinal scanner, etc.). An alphanumeric keypad 236 (similar to thoseused on telephones) may also be utilized to enter identifyinginformation about the stun device SD or user. In alternativeembodiments, the keypad may be a complete keyboard typically utilized ona computer, either built into the tester or remote therefrom andconnected by a cable. In other embodiments, a touch screen or voicerecognition system having a graphical user interface may also beutilized.

The tester 202 provides information and feedback to a user via one ormore integrated or remote components. For example, a display screen 238may be utilized to present instructions, images of discharge waveforms,results, or other data to a user. In certain embodiments, the displayscreen 238 may be incorporated with the touch screen described above.One or more LEDs 240 may be used to provide simple instructions orfeedback (e.g., “Proceed,” “Fail,” “Continue,” “In Spec,” “Out of Spec,”etc.), and a piezoelectric sounder or other sound generating device mayalso or alternatively be utilized. Additionally, output from theprocessor 230 may be delivered to a remote oscilloscope 242 or signalanalyzer for further research, analysis, or testing purposes. The tester202 may send certain results to a printer 206, which, in certainembodiments, may be integral with the tester 202. Such an integralprinter may be similar to a register printer that prints to a ribbon ofpaper media. The tester 202 may be a stand-alone device or may beconnected directly to a network or internet connection 210, as describedabove. A stand-alone computer 204 may also be connected to the tester202 to collect, process, and/or store test data, or to providediagnostic testing of the tester 202 itself. As described above withregard to FIG. 4A, the computer 204 may be connected to a stand-aloneprinter 206 a, and/or a network 210 a.

FIG. 5B depicts a schematic block diagram of a stun device testingsystem 250 in accordance with another embodiment of the technology. Astun device SD is inserted into a port 252 of the tester 250. The tester250 includes a resistor/relay module 254. The resistor/relay module 254is in communication with a processor 256. A single board computer 258integrates the function of a wireless transmitter 260, a touch screen262, as well as a barcode scanner 264. Additionally, the tester 250 mayalso include one or more environmental modules 266 (as described furtherbelow). In certain embodiments, it may be desirable for theenvironmental module 266 to be downstream of an air intake fan 268 tohelp ensure accurate readings.

FIG. 6A depicts a schematic diagram of a stun device testing apparatus300 in accordance with another embodiment of the technology. The testingapparatus 300 may include a stand-alone tester 302 that includes thecircuits to test various stun devices SD. Additionally, the tester 302may be connected to one or more adapters 350. Each adapter 350 may bemanufactured to mate with the discharge end of a particular stun deviceSD via a coupling 352, and may include a common connector 354configuration. The adapter 350 may include a voltage divider 356 withinthe adapter housing 358, as well as the stun device coupler 352. Incertain embodiments, the voltage divider 356 may be utilized when themaximum voltage of a stun device is too high for the tester circuitry,and must be reduced to accommodate the measurement and prevent damage tothe tester. While a voltage divider may not be required for severalknown devices on the market today, other devices exist or may bedeveloped with specific characteristics that require modification formeasurement on the safety tester. In certain embodiments, the voltagedivider may be incorporated directly into the tester 302, as opposed tothe adapter housing 358.

The coupler 352 connects the output leads of the device SD to theadapter 350. A coupler may be manufactured for each known stun device onthe market or, alternatively, a universal coupler may be utilized toreduce costs associated with multiple custom couplers. Specificallyconfigured couplers (or adapters, if the coupler is directly integratedinto the adapter) may be required, because stun devices varydramatically in form-factor. Some are large or small handgun formats,some are batons, and others are rectangular shapes. Some stun deviceshave protruding prongs and some utilize flat contact strips.Projectile-dart based stun devices should be measured with the dartaccessory in place, as well as with the accessory disconnected, toverify output of the device when the external device contacts arepressed directly against the skin or penetrating the skin surface. Inaddition, the adapter 350 provides a high insulation factor to guardagainst electrical shock to the operator, since stun devices often havea high degree of arcing that can contact a nearby user during deviceactuation. Thus, an adapter/coupler combination is helpful to bothsecure a reliable connection to the tester 302 and to provide insulationto prevent electrical shock to users. The adapter or port may be liquidtolerant.

Specifically configured interfaces, ports, couplers, adapters may alsoinclude supports or other physical structure to ensure proper alignmentbetween the stun device and the tester. An exemplary, removableinterface 400 is depicted in FIG. 6B. The interface 400 includes afaceplate 402 secured to a receiving port or housing 404. Two compliantmembers or spring contacts 406 are secured within, and extend from, thereceiving housing 404. Compliant members 406 (e.g., springs) help ensurecontact between the contact tips 406 a and the discharge elements 408located on the stun device SD. The interface 400 may include a dockingstation or shelf 410 that provides reliable stun device SD placement andalignment. In certain embodiments, it may also enable the user torelease the stun device SD during testing for safety purposes. Theinterface 400 may be secured to the tester 412 with screws, bolts,magnets, latches, spring clips, or other releasable coupling elements414. Interfaces may be readily removable from the tester, allowing anumber of interfaces adapted to receive specific stun devices to be usedwith a single tester, thereby reducing manufacturing costs.

The spring contacts 406 are connected to an interface connector 416adapted to mate with a tester connector 418 located on the surface ofthe tester 412. The tester connector 418, in turn, may be wired to a PCBconnector 422. The PCB connector 422 connects to a PCB 424 that performsthe waveform testing and analysis. Utilizing a removable connection atthe PCB enables an operator to remove the PCB 424 from the tester 412for testing and servicing. Alternatively, a non-removable PCB may beutilized and the tester may be itself tested or updated via a USB port,a network connection, etc. The configuration depicted in FIG. 6B allowsdifferent types of stun devices to be tested on the same tester, but thetester of the present technology could also be manufactured with adedicated built-in interface configured for a single type of stundevice. Other types of interfaces are also contemplated to test stundevices and stun guns that deliver electric waveforms utilizing launchedprojectiles. Since launched projectiles typically utilize barbs tosecure to a target, interfaces that utilize compliant or perforatedmaterials that may be penetrated by barbs are contemplated. Suchinterfaces may utilize screens manufactured of conductive materials,conductive rubbers or plastics, etc.

Returning to FIG. 6A, the depicted testing apparatus 300 may include adisplay screen 338, that allows a user to view waveforms WE of the stundevice SD discharge or other information. In certain embodiments,discharge periods for analysis can range from 1 to 45 seconds,simulating conditions of contact in the field during actual use. Such asignal capture feature P could be included along with other specificmodes of signal capture and analysis for stun devices, and certain dataregarding the discharge or the tester itself may be displayed for theoperator on a second data display screen 338 a. The displayedinformation may be used to aid an operator of the tester in making adetermination regarding the operation of the stun device SD beingtested, or regarding the operation of the tester 302 itself In certainembodiments, however, the potentially subjective decision-making processof a human operator is bypassed in favor of a decision made by thetester 302 or an associated computer regarding the suitability ofoperation of a stun device SD. In such a case, one or both of the datadisplay screens 338, 338 a may be omitted from the tester 302 orreconfigured to display a status result (e.g., “OK to Use,” “DO NOTUSE,” etc.).

Another feature that may be incorporated in the stun device testingapparatus 300 is the capability to measure current leakage and/orelectrical breakdown from the stun device SD itself An electricalcable/lead 340 extending from the tester housing 342 may be attached tothe stun device SD to measure leakage by the apparatus 300. Informationregarding the leakage may be displayed to a user via a leakage display344 or one of the other display screens 338, 338 a on the tester 302.Leakage or breakdown is dependent, in part, on the location and area ofthe contact providing the leakage or breakdown path, and is important tothe operator of the tester 302, to prevent the operator from beingincapacitated by the discharge during testing. Also, leakage canindicate a malfunction of the stun device SD. Again, not all informationregarding leakage or breakdown need be presented to an operator. In sucha case, the leakage display 344 may be omitted from the tester 302, andthe tester 302 or the associated computer may make the necessarydeterminations regarding the safe operation of the stun device SD. Inone embodiment, the type of leads utilized for EKG analysis ofdefibrillators and pacemakers may be employed to measure leakage. Theapparatus 300 may also provide waveform analysis for a number of loadconditions to simulate contact with differing parts of the body withdiffering intrinsic resistance and capacitance characteristics. Undersuch conditions, the internal circuitry of the stun device SD can behavein a consistent fashion to conserve the waveform for the purposesdescribed previously.

The stun device testing apparatus 300 may also feature output from stundevices as compared against a variety of known and accepted electricalsafety standards for electrical devices and for biomedical devicesspecifically. The apparatus 300 may incorporate one or more comparisonoutputs 346 a, 346 b, each offering a visual display or otherrepresentation of acceptable comparison and verification by the user.The testing apparatus 300 also may record individual waveforms anddetailed time and date information of the tested device, and comparethat information with standards based on the manufacturers'specifications, previously recorded discharge characteristics of thespecific device, standards of other known devices, etc.

FIG. 6C depicts a partial perspective view of an interior portion of ahousing 452 for a stun device testing apparatus 450 in accordance withone embodiment of the technology. Notably, the housing 452 includes anopening for receiving an airflow from the exterior of the housing 452.The airflow is drawn into the housing 452 by a fan 454. An environmentalmodule 456, which may include at least one of a temperature sensor, abarometric pressure sensor, and a humidity sensor, or combinationsthereof, is disposed downstream of the fan 454, such that the airflow isdirected over the environmental module 456. In certain embodiments ofthe various testers described herein, it may be advantageous to detectand record ambient environmental conditions, which can have an effect onthe testing protocols and/or test results. By locating the environmentalmodule 456 downstream of the fan 454, the ambient temperature andhumidity, for example, may be detected without the reading beingdetrimentally effected by heat and temperature variations due tocomponents within the housing 452. The environmental module 456 ismounted on a header which spaces the environmental module 456 off themainboard and into the airstream of the fan 454. This helps ensure thatoutside temperature, not inside temperature, is read.

FIG. 7A is a schematic diagram of a hardware configuration of a stundevice testing apparatus 500 in accordance with an embodiment of thetechnology. A device under test (DUT) 502 (i.e., an electric waveformdelivery device) is connected to a load 504, which accomplishes at leasttwo goals: 1) a well-known voltage and current waveform can be producedby the use of Ohm's law (Voltage=Current×Resistance), and 2) the highvoltage signal level from the DUT 502 will be reduced to a level that isnot damaging to the analysis circuitry contained within the testingapparatus 500. In one embodiment, a network of resistive devices may beutilized, e.g., the resistive values of an exemplary network may be 100,250, 500 and 1000 ohm. Each different resistive value may be attached toa computer-controlled relay that may be either mechanical or electrical,depending on the anticipated energy level of the discharge impulse. Theresistor and relay network is designed such that they are not mutuallyexclusive, thereby allowing a wide range of restive values with minimalimpact on device size and cost.

The load 504 is connected to a current monitor 506, which outputs avoltage that is proportional to the current through the load 504. Thevoltage output of the current monitor 506 is then input to the printedcircuit board (PCB) 508. The input signal is first conditioned 510 tomatch the input requirements of the digitizer (an analog to digitalconverter, A/D) 512. This conditioning includes several specificfunctions, including input filtering, digital attenuation, high-gainoperational amplification (op-amp), and conversion operationalamplification. Input filtering limits the noise bandwidth at the inputto the A/D. Digital attenuation combines with the gain from thefollowing stage (high gain operational amplification) to match the inputsignal level to the full-scale level of the A/D. In one embodiment, thisattenuator has a range from about 1.0 dB to about 16 dB, which may beset via commands to a processor 514 or through the use of an on-boardswitch. The high-gain op-amp circuit is designed for a voltage gain ofabout ten. Coupled with the input attenuator, the output of thisamplifier can be typically in a range of about 0-2V nominally. Finally,a single ended-to-differential conversion op-amp converts the signalinto differential format and has an added level shift, since theoriginal signal is DC-coupled.

In one embodiment, the AID 512 operates at 100 MS/s (million samples persecond) with a resolution of 16 bits. This configuration provides theuser with the ability to “see” the waveform in 10 nanosecond steps intime, with a total of 65,536 steps in discharge intensity. The output ofthe A/D 512 is passed directly to the processor 514 (which, in certainembodiments, may be a field programmable gate array (FPGA)), usinglow-voltage differential signaling (LVDS). FIG. 9A depicts oneembodiment of a circuit 630 utilized in the hardware configuration ofFIG. 7A for load 504, the current monitor 506, the signal conditioner510, and the AID 512.

Returning to the hardware embodiment depicted in FIG. 7A, the FPGA 514may be manufactured by Xilinx, Inc. FPGAs allow for a wide range of datamanipulation techniques while being field re-definable for futureproduct upgrades, features, enhancement, etc. Use of an FPGA 514provides the option of elimination of external computer control(provided sufficient processing capability is present) of the testingapparatus 500. In that case, the FPGA can perform all of the dataanalysis internally, handle user display functions, etc. If an externalcomputer is utilized, however, the FPGA may be utilized only forancillary functions, such as data handling and communicationsscheduling. VHDL code can be utilized to accept data from the AID 512continuously while being stored in an internal or external memory array.Additionally, the FPGA 514 can accept commands to stop/start a test,capture data, switch resistive loads, etc. The FPGA 514 also handles allUSB 516 communications from the computer running the graphical userinterface. In certain embodiments, the communications interface may bedefined by the USB 2.0 standard, which is robust, familiar, and readilyavailable in most consumer-based computing electronics.

FIG. 7B depicts an exemplary embodiment of a FPGA 514 utilized incertain embodiments of the technology. The A/D 512 delivers output to aninput memory device 520 that, in the depicted embodiment, is a firstin/first out (FIFO) memory to compensate for the differing clock speedsbetween the A/D clock and the USB clock 526, described below. Outputfrom the input memory device 520 is delivered to both a storage device522 as well as a peak detection device 524. The storage device 522 isalso a FIFO and is described in more detail below, in conjunction withother related elements. The peak detection device 524 determines whenthe waveform discharged from the DUT 502 reaches a peak signal,initiating storage of the waveform information. This data is in turnoutput to the USB memory device 526, USB interface 528, and USB clock530. In certain embodiments, the USB memory device 5256 may be a FIFO.The USB interface 528 changes the clock domain to the USB standard clockfrequency, which is necessary to avoid loss of data for data sampled athigh rates. For example, certain embodiments of the tester may sampledata at 105 MHz, significantly faster than the USB clock.

Storage device 522 and USB memory device 526 provide memory space forstoring data samples received from the A/D 512. In one embodiment, thestorage of the incoming data samples is triggered when the peakdetection circuit 524 detects a peak in the incoming waveform. Eachsample may represent a fixed amount of capture time, for example, 10nanoseconds (ns). Because the storage device 522 and USD memory device526 contain a finite amount of storage space, the size of the storagedevice 522 and USD memory device 526 sets an upper limit on the totaltime a waveform may be captured. For example, if the storage device 522and USD memory device 526 store 100 data samples, the total time is100×10 ns=1 microsecond (μs). In one embodiment, the storage device 522and USD memory device 526 store 64,000 samples, providing 640 μs oftotal data capture time. Also stored in the FPGA 514 are a number ofregisters 532 that control operation of the apparatus. These includepeak detection registers 532 a that control the capture of waveform dataassociated with the peak, and load control registers 532 b thatdetermine the testing load based, at least in part, on the type (i.e.,manufacturer, model, etc.) of the DUT 502. Additionally, reset/startregisters 532 c control when data is taken, when the device is reset,when data capture stops, etc. In one embodiment, the FPGA 514 is able tobe re-programmed via the USB interface 528.

The testing apparatus disclosed herein may be a stand-alone apparatusrequiring no connection to a computer. In that case, the processor mayrun all the necessary analysis and present the required data/info via ascreen or other components. In embodiments of the apparatus 500 thatinclude an external computer 518, a LABVIEW™-based graphical userinterface (GUI) may be utilized. LABVIEW software is available fromNational Instruments Corporation, of Austin, Tex. Other types ofsoftware that may be utilized include Mathematica and MatLab. TheLABVIEW-based programming may be compiled as an .exe executable file,allowing operation on any Windows-based PC (or Intel-based Macs). Ifdesired, the data displayed to the user may be a subset of the totaldata analyzed, such that the user is not confused by an overload ofdetails or provided unnecessary information to perform his job. Theapparatus may provide the option of delivering more information to theuser for more advanced purposes.

During use, when the user selects the stun device to be tested, theprogram automatically switches to the correct load resistance for thatstun device. The user may scan the stun device barcode or enter the stundevice serial number, thus initiating a program to look up theappropriate load resistance, which may be stored locally or over aremote network. Raw data may be imported from the memory array into theprogram for analysis. While any waveform characteristics may beanalyzed, capture and analysis of energy delivered, pulse duration, peakcurrent, and frequency, are desirable for most stun devices. Theresultant data may then be compared to known values for the particulardevice, and the testing apparatus may provide a pass/fail indication tothe operator. The waveform and any desired data can be displayed on theuser interface. LABVIEW supports saving data locally in a specifiedlocation and format, but it may also be desirable to upload the data toan internet database.

In various embodiments of the GUI, a drop down menu may be utilized forthe operator to select which stun device is to be tested, or the stundevice barcode may be scanned, as described above. The GUI also mayutilize areas for data entry, such as serial number, customer name, testoperator, etc. A pass or fail indication will illuminate after the datahas been analyzed. The waveform may be displayed along with somecalculated data such as frequency, peak current, etc., if desired. Ifavailable, the stun device manufacturer's expected waveform can bedisplayed next to the tested device waveform for a visual pass/failconfirmation. A data print out option may be available for printersconnected to the computer 518.

As described above with regard to the embodiment of the tester 102depicted in FIG. 4A, multiple ports are utilized on certain embodimentsof the stun device tester. The multiple ports may be used to determinean electrical terminal model of the stun device. A terminal model is aconceptual embodiment of a mathematical equation that relates thevoltage and current at a terminal pair or port of an electrical circuit.In general, a complex electrical network can be divided into a sourceand a destination connected by a pair of wires (otherwise known as aport). The source, destination, and even the wires themselves areconceptual. Connecting the source and destination ports constrains thevoltage across the wires and the current through the wires to be equal.In mathematics, this is equivalent to solving two equations for twounknown quantities. Consider an example where the source is a stundevice that can develop 10,000 volts and a target of approximately 50ohms resistance. The current developed into the target determines themagnitude of the electric field within the target's body. Assuming thestun device has a very low source resistance, then the prediction mightbe 10,000 volts/50 ohms=200 amp current. If the assumption is that theresistance of the stun device is 1,000,000 ohms then the current is10,000 volts/1,000,000 ohms=0.01 amps. Both are assumptions.Accordingly, it is desirable to know the current. Based on testingperformed, observed currents in the range of 1 to 10 amps suggest sourceresistances of 1000 to 10,000 ohms. Determination of an electricalterminal model utilizing multiple ports of the exemplary tester depictedin FIG. 4A is described below.

FIG. 8A is a schematic block diagram of a hardware configuration of astun device testing apparatus 600 in accordance with another embodimentof the technology. A device under test 602 (e.g., a stun device) isconnected to a resistor pack 604 through spring contacts as describedherein. The spring contacts help ensure connection by engaging thedevice under test 602 prior to the device under test 602 being fullyseated in a receptacle that receives the device under test 602. Theresistor pack 604 presents a minimum load of 1000 ohms regardless ofwhether the tester 600 is powered or unpowered. Presentation of aminimum (or default) resistance load is a safety feature that preventsinadvertent damage to the tester 600 and/or injury to a user, should thedevice under test 602 be discharged into an unpowered unit. The load canbe changed depending on the protocol being used to test the device undertest 602, as controlled by the single board computer 606 (SBC). Theoutput of the resistor pack 604 is a voltage reduction of about 100:1,but other voltage reductions may be utilized. The resistors locatedwithin the resistor load pack 604 are calibrated, which allows thetester 600 to calculate voltage and current discharged from the deviceunder test 602 accurately.

A signal conditioner 608 is used to filter a discharge waveform as wellas apply different gains depending on the device under test 602. Thedischarge-receiving circuit disposed in the signal conditioner may behigh-voltage protected as an additional safety feature. A digitizer 610samples and stores 64 million 12-bit samples. In one embodiment, thesampling rate is 10M/second. Thus, 6.4 seconds worth of data iscollected. Other sampling rates may be utilized. In this embodiment, theSBC 606 is not utilized in any real-time data collection, thus reducingor eliminating the possibility of missing data due to software issues.The SBC 606 retrieves the data from the digitizer 610 and applies gainand offset corrections (which are programmed into the digitizer 610)prior to data analysis. The data analysis, as well as the raw data, maybe compressed and/or stored on the SBC 606 until a data package istransmitted to a designated remote storage (for example, a computer,remote database, etc.). This data may be transmitted via a wirelessmodule 612 or by a cabled connection. Once stored remotely, the raw datacan be deleted from the tester 600 to conserve memory.

FIG. 8B depicts functions performed by the hardware configuration ofFIG. 8A. A stun device testing apparatus 620 utilizes digital processingin the digitizer 610 that includes a complex programmable logic device622 (CPLD). The CPLD 622 may perform one or more of the followingfunctions. The CPLD 622 may control operation of the A/D converter 624,as well as signal conditioning circuitry gain from the signalconditioner 608. Additionally, the CPLD 622 may control operation of theresistor pack relays in the resistor load pack 604. If a USB chip isutilized, the CPLD 622 may control the interface 626 to the USB chip.Data flow between the AID converter 624 and the SDRAM 628 may also berouted through and otherwise controlled by the CPLD 622. Data flowbetween the SDRAM 622 and the USB chip, via the USB interface 626, maybe similarly routed and controlled. Additionally, the CPLD 622 maydetermine when data storage to the SDRAM 628 will begin, and the CPLD622 may deliver a predefined test pattern to the SDRAM 628 to be used asbuilt-in test equipment. In a particular embodiment, when initiated bythe SBC 606 over the USB interface 626, the CPLD 622 monitors theincoming data from the A/D converter 624. When the data exceeds anabsolute value as defined by the test protocol, the CPLD 622 thendirects data to the SDRAM 628 until a full 6.4 seconds worth of data iscaptured. This data is then sent to the USB chip for use by the SBC 606.

FIG. 9B is a schematic diagram of a circuit 650 utilized in a stundevice testing system in accordance with one embodiment of thetechnology. The depicted circuit 650 receives and processes waveformsdelivered from a multi-port testing apparatus, such as that depicted inFIG. 4A, but components of the circuit 650 may also be used in othercircuits and testing apparatus described herein. The testing proceduresdescribed below may also be utilized in various embodiments of thetesting system described herein. Components include a LABJACK digitalI/O, a Cleverscope C328A Digital Oscilloscope, an Avertec laptopcomputer, an HP Laserjet printer, a Zvetco finger print reader, aPhidgetUSA RFID reader, and a Belkin USB hub. All of these componentsare commercially available and communicate via a USB connection.Discrete electronics are limited primarily to driving LEDs andresistor-capacitor networks that match the signal received in the portsto the requirements of the digital oscilloscope. This latter requirementis further minimized by the digital oscilloscope's ability to detect andadjust itself to the presented signal. These components require nodirect observation or contact by the user, although certain embodimentsof the device may include options for such direct, contemporaneousobservation. The digital oscilloscope operates as a data acquisitiondevice which is observed and controlled by the connected personalcomputer. The LABJACK interface can generate control signals for theLEDs that guide the user during operation, as described above. Theapparatus can also sense contact closures to allow simple signaling fromthe user, to sense proper positioning of the stun device in the ports,etc. Two modes of operation may be used, one high-speed sampling mode tocapture spikes, transients and normal waveform, and a second to assesstemporal patterns upon stimulus triggers of about 10 msec pulse, whichis sampled and stored as a waveform. All data from a Liven test is thenexported to a computer where detailed comparisons with stored andarchival data can be made using appropriate software. Exemplary softwarecan include statistical analysis software programs, such as SYSTAT™,manufactured by Systat Software, Inc., of Chicago, Ill. or MATLAB™,manufactured by The MathWorks, Inc., of Natick, Mass. Other componentmanufacturers may provide components utilized in the manufacture of thetesting device. The above description does not limit similarconfigurations using different components.

Virtually any characteristics of the electric discharge may be measured,recorded, and analyzed by the device. While the most accurate testersmay measure, record, and analyze a significant amount data regarding awaveform, more limited analysis of the waveform may be possible based ona smaller number of characteristics. In addition to capturing an imageof the waveform, additional data regarding the discharge may also becollected. Certain embodiments of testing devices may test for one ormore of an amplitude, a duration, a current, a voltage, an energy, or atemperature associated with the discharge. Additionally, other data mayinclude: 1) joules per pulse, 2) total joules, 3) peak, average currentfor at least two different loads, 4) open-circuit voltage, 5) featuresof spark gap variability, etc. Waveform anomalies to be captured mayinclude: 1) fast spikes, amplitude, rise-fall time, 2) differences inwaveforms, rms, peak-to-peak, peak difference, 3) rate 5 to 60 pps, 4)variation in rate, 5) burst rate (patterned bursts), 6) duration ofstimulus delivery, 7) measured battery voltage and predicted number ofdischarges based on battery voltage, 8) temperature of measurement log,etc.

The technology disclosed can be utilized in a variety to ways to verifya manufacturer's claim of specific waveform characteristics and as anindication of the safety of a given waveform. In the case where amanufacturer's claim of a specific waveform and linked safety or injuryoutcomes are defined, the disclosed technology can compare the waveformas measured against the manufacturer's reported waveform. A suitablecomparison can be made in a variety of ways. In one embodiment, thetester can contain a software-based library of waveforms (as reported bythe manufacturer) with established thresholds for uncertainty for theprimary components of the waveform. For example, the peak current of awaveform is one diagnostic that should remain relatively constant acrossvarious loads. An uncertainty of, for example, about ±0.5A can beestablished as representing an acceptable deviation from the standard,reported waveform. Higher deviations then can be flagged as outliers andsignal can be delivered that the device under test may not be inspecification as reported by the manufacturer. Similarly, waveformcharacteristics such as peak voltage, energy per pulse, cumulativecurrent, energy, etc., can be characterized by “correct” values (i.e.,conforming to manufacturer's specifications) and acceptable orunacceptable uncertainties (i.e., deviating from the specifications byan acceptable or unacceptable amount).

Additional features of stun devices, such as frequency, intensity, etc.,can be combined creating classes of calculations that can also bemeasured, calculated, and defined by acceptable or unacceptableuncertainties. In the case of frequency, for example, deviations ofapproximately plus or minus 5 Hz, could be considered off ofmanufacturer's specification. When considering the intensity of awaveform, which in one embodiment may be defined as peak values forvoltage or current and pulse duration, a similar comparison can be madereferring to a reference waveform and deviations therefrom. In theforegoing cases, one example of comparing the manufacturer's stated orclaimed waveform to that of a device under test can employ mathematicaland statistical comparisons of data components versus load for both areference and waveform for a specific device under test. Suchcomparisons can generate plots of each component versus load, forexample (i.e., peak current versus load, peak voltage versus load,energy per pulse versus load, etc.). Some examples of waveform testingare described in Savard, P., Walter, R., and Dennis, A., “Analysis ofthe Quality and Safety of the Taser X26 devices tested forRadio-Canada/Canadian Broadcasting Corporation by National TechnicalSystems,” Test Report 41196-08.SRC (Dec. 2, 2008), the disclosure ofwhich is hereby incorporated by reference herein in its entirety. Inanother embodiment, current root mean square (rms) values can becalculated and converted into appropriate units as defined by the“Effects of Current on Human Beings and Livestock,” IEC Publication479-1, 3d ed., (1994); and “Effects of Current Passing Through the HumanBody,” IEC Publication 479-2, 2d ed., (1987). These may then be comparedto known rms values and pulse durations of other waveforms to establishsafety thresholds for ventricular fibrillation. It is anticipated that,as new standards of safety for stun devices are developed, the disclosedtester can promptly employ such data and software to serve as a safetycomparison with a device under test. Thus, the disclosed tester canoffer a means to statistically compare a measured waveform with aclaimed reference waveform and a means to determine the safety of agiven waveform compared to established methods. In addition to comparingthe waveform discharged by a device under test to a known manufacturer'sstandard waveform, the tester can also compare a waveform of a stundevice of unknown origin to a database of known waveforms. Thiscomparison can allow the tester to characterize a discharge waveform aspotentially safe or unsafe by comparing its characteristics to those ofother tested waveforms or manufacturer's standard waveforms that havebeen determined previously to be safe or unsafe.

EXAMPLE

FIGS. 10A-14H, as well as FIGS. 15A-17D, depict particular constructiondetails of but one example embodiment of a stun device testing system.The figures and associated text are presented as an example only, asother configurations are also contemplated.

FIGS. 10A-10C depict a block diagram of a hardware configuration of astun device testing apparatus 700 in accordance with another embodimentof the technology. The front end board is a printed-circuit assemblythat performs the analog data acquisition and control functions for thetester. This board contains a high speed analog-to-digital converter(ADC) configured to measure high voltage pulse waveforms, memory chipsto store the acquired waveforms, a complex programmable logic device(CPLD) to manage conversion and transmission of the results to anexternal processor, environmental sensors, power converters, and a USB2.0 (Universal Serial Bus) interface chip. The board is used withcommercial off-the-shelf (COTS) assemblies to create the hardware forthe tester 700: processor board (Advantech MIO-2261), WiFi board andantenna, touch-screen liquid-crystal display unit, touch-screeninterface board, bar code scanner, and SQF compact Flash storage.

FIGS. 10A-10C also depict a table of power consumption by supply voltageand schematic page and a full-board parts list, in addition to thetester system block diagram 700. The tester system 700 includes aninterchangeable test fixture (“holster”) that accepts a variety ofelectro-shock weapons. The weapon is inserted into the holster andtriggered by the user based on prompts from the display. Thehigh-voltage pulse signal is terminated in a relay-selectable 3-valueload resistor network on the holster, and conditioned by a four-rangefractional-gain amplifier with high-voltage protection to create ananalog signal in the ±2-volt range. This is fed to a 12-bit 10mega-samples-per-second (MSPS) ADC to generate a bipolar digitalrepresentation of the measured voltage every 100 nanoseconds. The ADCoperates continuously on the signal from the test fixture. On commandfrom a control register, when the ADC output indicates that the weaponis firing, 6.4 seconds of samples (64,000,000 samples) are stored in apair of memory chips (Synchronous Dynamic Random-Access Memory, SDRAM).At the end of the acquisition period, the processor board reads the datain 32 k word blocks via a high-speed USB 2.0 link for furtherprocessing. A CPLD manages the memory timing, the acquisition of theblock of data, and the transmission of the blocks to the processor.

A pair of environmental sensor chips (also referred to herein asenvironmental modules) measure ambient temperature, humidity, andbarometric pressure. The results are transmitted to the CPLD by SPI(Serial Peripheral Interface), and are made available in USB-readableCPLD registers. Power to the unit is routed through a filter/rectifiernetwork and a buck-boost power converter, so any input voltage between12 and 24 volts of either polarity can be used without damage orinterruption. This supplies regulated 12 volt power to the MIO-2261Processor Board. Once powered-up, the MIO in turn supplies the +5 voltpower demand of this board via the USB port. Other power conversion andfiltering stages on this board convert USB +5 volt power to digital +3.3volt power for the CPLD and quiet bipolar 5 volt analog supplies for theADC. Also in the tester system 700 are a precision reference voltage forthe ADC, a small electrically-erasable programmable read-only memory(EEPROM) to configure the USB interface and store software calibrationconstants, a 12 megahertz (MHz) crystal oscillator for the USB chip thatproduces a 60 MHz system clock, a Joint Test Action Group (JTAG) testport for in-system programming (ISP) and testing of the CPLD, and a setof diagnostic light-emitting diodes (LEDs). The components depicted inFIGS. 10A-10C are described further in FIGS. 11-14H below. FIGS. 11-11Fdepict a schematic diagram of a front end circuit 704 utilized in thehardware configuration of the tester 700 of FIGS. 10A-10C. FIGS. 11-11Fdepict the circuitry to scale the input signal, the ADC and itsreference, and a set of digital output registers to present thedigitized signal to the CPLD.

High Voltage Divider. A high-voltage tolerant non-inductive resistornetwork at the holster terminates the high-voltage signal to simulatethe load of a human subject. The value of the load resistor isselectable using a pair of relays. With both relays open, the loadresistance is 1 k ohm. With the LOAD600 relay closed, the loadresistance is 600 ohms. With the LOAD200 relay closed, the loadresistance is 200 ohms. The resistor network divides down thehigh-voltage signal by a factor of 100 to a maximum of ±100 volts so itcan be handled on the front-end board.

Protected Differential Input Amplifier. The leads from the holsterattach to connector J1 at the high-voltage end of the circuit board. Thedivided voltage is fed through resistors R2 and R4 to a differentialamplifier made from a high-speed operational amplifier (opamp) U1B,where feedback action keeps the opamp input terminals close together andwithin ±2 volts of ground. This keeps the high voltages out of theremainder of the circuit. In the event of an out-of-range voltage input,back-to-back diodes within the opamp combined with the high (100 k ohm)resistance of the resistor chain work to clamp the voltage spike andprevent it from damaging any of the semiconductor circuitry. U1B isarranged as a differential amplifier with a fractional gain of 0.02(1/50) to the incoming analog signal. In combination with the 100:1division at the holster termination network, this gives a total gain of0.0002 (1/5000) to the input stage. Capacitors C6 and C7 limit thefrequency response of the amplifier to 17 MHz to limit noise and preventoscillation. For the maximum input range of ±10 kilovolts, U1B output isin the ±2 volt range.

Range Selection Amplifiers and Relays. This signal is fed to a pair ofnon-inverting amplifiers U1C and U1D with a combined precision gain of1, 2, 5, or 10. Gain is selectable with two long-life reed relays,driven by Q1 and Q2 with signals from the CPLD. When the relay isclosed, the stage is a noninverting amplifier with gain determined bythe resistors. When the relay is open, the stage becomes a unity-gainfollower. When the input range is ±1 kilovolt, the output of U1B is ±200millivolts. Both relays are closed, so U1C has a gain of 5 and U1D has again of 2 to boost the signal to ±2 volts. When the input range is ±2kilovolts, the output of U1 B is ±400 millivolts. K1 is closed so U1Cstill has a gain of 5, while K2 is open so U1D now has a gain of 1, andthe signal is boosted to ±2 volts. When the input range is ±5 kilovolts,the output of U1B is ±1 volt. K1 is open so U1C now has a gain of 1,while K2 is closed so U1D still has a gain of 2, and the signal isboosted to ±2 volts. When the input range is ±10 kilovolts, both relaysare open so the gain amplifiers have a combined gain of 1, and thesignal remains at ±2 volts. At power-up, both relays are open to selectthe lowest gain and highest range. So the output of U1D is in the±2-volt range regardless of the input range. All stages arenoninverting, so the output signal has the same phase as thehigh-voltage input. Since the actual input range of the ADC is ±2.048volts, there is a 2.4% headroom to allow software to calibrate outaccumulated errors. If the wrong range is selected, the output voltageof U1D either will be too low, or will clamp at the power supply rails.So the reading will be wrong but no damage will be done. The output ofU1D is fed into a simple 18 MHz filter consisting of R10 and C10 tosuppress high-frequency noise.

Analog to Digital Converter. U2 is the ADC, an LTC1420C from LinearTechnology. This chip is designed to convert at a maximum rate of 10MSPS. It is clocked at 10 MHz and does a conversion on every clockpulse. The conversion is pipelined so that the value presented at thedigital outputs is 3 clocks behind the analog input value, but this isof no consequence since the converter operates continuously. The outputof the ADC is a 12-bit two's complement binary number, with anadditional overflow bit to indicate if the input signal is out of range,meaning that the output value is unreliable.

Output Registers. The output word is fed to a pair of 74LCX574 tri-stateregisters. The output word is registered using the same 5-volt clock asthe ADC. The register outputs are presented to the CPLD and SDRAM. Atest mode (described later) uses a signal from the CPLD to tri-statedisable the outputs of the registers, so the CPLD can substitute apredictable test count pattern for storage into the SDRAM. This allowsfor easier debugging.

Analog Grounding. The ADC and opamps operate from ±5 volt analogsupplies, filtered to keep supply noise low. A separate analog ground(AGND) is used to prevent digital switching currents from circulating inthe ground plane and causing errors in the reading. This AGND isconnected to the digital ground at only one point, zero-ohm resistorR12. The PC board ground and power planes are split between digital GNDand AGND to prevent capacitive interaction and noise transfer betweenanalog and digital signals and supplies.

Voltage Reference. Although the ADC contains a stable internal referencevoltage circuit, its absolute accuracy can be improved by providing anexternal precision reference voltage source (U5). U5 is an LT1461AC-4from Linear Technology; its 4.096-volt output is pre-trimmed to ±0.04%absolute accuracy. This is buffered by U1A with a gain of +1 and fedinto the ADC's reference voltage input. The buffer amplifier helpsisolate the reference from the low (1 k ohm) input impedance of the ADC,and from any switching currents present at the ADC input. The ADC isarranged so that the output code represents 1 millivolt per count, from−2.048 volts to +2.047 volts.

Calibration. Even though U4 is very accurate, there are accumulatederror sources throughout the circuit (such as resistor tolerances andADC inaccuracies) that can add up to produce significant errors in boththe full-scale (range) reading, and the zero-volts-in (offset) reading.So calibration runs are used to determine appropriate softwarecalibration factors for each range, which are then stored in the EEPROM.To calibrate the circuit, the highest range is selected. Thehigh-voltage input terminals are connected together and the softwareoffset value for a zero reading is adjusted. Then a precision +100 voltreference is connected across the high-voltage input terminals, and thesoftware range value is adjusted for a reading of +2.000 volts (0x7D0).This procedure is repeated with the other three ranges using theappropriate input voltages of +50, +20, and +10 volts.

ADC Clock. A 3.3-volt 10-MHz inverted clock from the CPLD is generatedwith the proper phase so that the register output word appears withadequate timing margin to be captured by the SDRAMs and CPLD. This3.3-volt clock is inverted and amplified to 5 volts by U6, a 74VHC1GT04level-shifter gate, and fed to the ADC and output registers. The ADCuses a 5V-level clock when running from bipolar supplies. The 74LCX574registers are guaranteed to be 5 volt tolerant at the inputs, allowingfor use of the same clock to recover the data as the ADC uses to produceit. This eliminates timing delays and allows the ADC to run at itsmaximum speed.

FIGS. 12-12I depict a schematic diagram of control circuit 706 utilizedin the hardware configuration of FIGS. 10A-10C. SDRAM, CPLD, and USBinterface. FIGS. 12-12I depict the SDRAMs used for storing the datablock, the CPLD that controls acquisition and transmission of the datablock, and the USB 2.0 interface chip that transmits the data to theprocessor.

Complex Programmable Logic Device. U8 is an EPM3512A CPLD from Altera.It contains 512 logic macrocells in a 208-pin package. It is programmedwith the logic via JTAG/ISP connector J2, but, unlike an FPGA, onceprogrammed it retains the data pattern when power is removed. The CPLDis clocked at 60 MHz and contains all the logic to manage the ADC,SDRAM, and USB FIFO: data acquisition and storage, data readout andtransmission, test mode, environmental sensor interface, andcontrol/status registers.

Synchronous Dynamic Random Access Memory Chips. U9 and U10 areMT48LC32M16A2P-75 SDRAMs from Micron Technology. Each chip is configuredas 33,554,432 (32M) sixteen-bit words and is clocked by the same 60 MHzclock as the CPLD. SDRAM is based on the familiar dynamic random-accessmemory (DRAM) chip architecture, but with a synchronous clockedinterface—so the input control signals such as RAS# and CAS# no longerasynchronously and directly strobe in addresses, but instead are set upto be active on a specific clock edge, and are encoded to operate theSDRAMs. The CPLD is responsible for managing the address, data, andcontrol input signals to the SDRAM (CS#, RAS#, CAS#, and WE#) to performthe required SDRAM functions of writing, reading, precharging,refreshing, and initialization. All accesses to the SDRAM are 16 bitswide, so the byte masking signals DQML and DQMH are strapped inactivewithin the CPLD.

An example CPLD clock diagram is provided for reference in FIGS.15A-15B. SDRAM Timing. The SDRAMs are operated on a fixed 200-ns periodconsisting of 12 clocks at 60 MHz. This allows time for one SDRAM reador write cycle per period. During data acquisition, a one-RAS two-CAStwo-single-writes cycle writes two 16-bit words into the SDRAMs. Duringdata transmission, a one-RAS one-CAS read-burst-of-two cycle reads outtwo 16-bit words from the SDRAMs. Doing two reads or writes in each 200ns period allows the peak throughput to be 10 MHz, same as the ADCacquisition rate; read and write use different timing mechanisms toallow for differing data setup time requirements. During refresh, threerefresh operations are accomplished in the 200 ns cycle.

SDRAM Write Cycle. For writing data, half of the address is presentedand CS# and RAS# are activated in time for the second clock edge. Thisis followed by the other half of the address, CS#, CAS#, and WE#activated for the fourth clock edge. The first word of ADC data has beenstable at the ADC register output and the bidirectional SDRAM data pinssince the first clock edge. That word is written into the SDRAM on thefourth clock edge. The address is incremented while the ADC updates thedata register with a new conversion result, and a second CS#, CAS#, andWE# are activated for the eighth clock edge, when the second word of ADCdata is written into the SDRAM. On the twelfth (last) clock edge of thecycle, CS#, RAS#, and WE# are activated to precharge all columns of theSDRAM in preparation for the next access.

SDRAM Read Cycle. For reading data, half of the address is presented andCS# and RAS# are activated in time for the second clock edge. This isfollowed by the other half of the address, CS#, and CAS# activated forthe fourth clock edge. The first word of read data appears as output onthe bidirectional SDRAM data pins on the sixth clock edge, when it islatched into a register within the CPLD. The address is incremented bothinternal and external to the SDRAM, and a second word of data is readfrom the SDRAM and latched into a second register on the seventh clockedge. On the twelfth (last) clock edge of the cycle, CS#, RAS#, and WE#are activated to precharge all columns of the SDRAM in preparation forthe next access.

SDRAM Refreshing. A read, write, or refresh operation occurs for each ofthe 8192 rows every 64 milliseconds to refresh the SDRAMs. SDRAM readcycles during transmission can only happen on alternate 200 ns memorycycles due to USB FIFO timing restrictions (see below) which allowsopportunities for a refresh cycle. However, acquisition uses everyavailable SDRAM write cycle during the full 5 second acquisition time.Since the SDRAMs are flat-out doing the write burst, there is no timeduring acquisition for separate refresh operations. Thus, the addressingof the SDRAMs has been arranged so that acquiring (or transmitting) ablock of data automatically refreshes the memory array. Address bits 1through 13 from the address counter select the row, address bit 14selects the chip, and address bits 15 and 16 select the bank address.That way, every time 128k words are sequentially written or read, all8192 rows, both chips, and all four banks within each chip arerefreshed. Address bit 0 can't be used for refresh; it needs to be theLSB of the column address so that burst (internally incremented) readaddressing matches non-burst (externally incremented) write addressing.

When the memory is not acquiring or transmitting data, a burst of threerefresh operations is performed on every 117th cycle (117×200 ns=23.4microseconds). For a refresh operation, CS#, RAS#, and CAS# of bothSDRAM chips are all activated for the second, sixth, and tenth clockedges of the 200 ns cycle. There is no need for a precharge after arefresh operation. The SDRAM chip internally takes care of incrementingthe refresh address, so all 8192 rows are refreshed every 2731 refreshcycles, or 63.9 milliseconds.

SDRAM Initialization. The SDRAM must be initialized on power-up. Asequence of initialization steps is performed by a counter in the CPLD:CKE is initially held low with refresh operations disabled, then afterthe power and clock are stable and a delay elapses CKE is set high andleft there, then a precharge-all is performed on both SDRAM chips, thenrefresh cycles are started, then after several refresh cycles haveoccurred the mode registers in both SDRAM chips are loaded via theaddress pins to select the operating mode (the value loaded is 0x0221,which selects standard single-access per CAS [not burst] write cycles,and a burst-of-two read cycle with a CAS latency of 2 clocks). Afterthis, the SDRAM is ready for normal data access operations, and refreshcycles continue on schedule.

Data Acquisition. The ADC is continuously converting the analog signalfrom the test fixture. When acquisition has been enabled in the controlregister and the CPLD is not acquiring or transmitting data, the CPLDcontinuously monitors the absolute value of the digital data from theADC and compares it to an internal programmable threshold register valuecontaining a positive data value. When the incoming ADC data exceeds theprogrammable threshold, signifying that the weapon has begun firing, theCPLD enters “acquiring” mode. In “acquiring” mode, two 12-bit ADC values(with the overflow bit appended in bit 15) are written into the SDRAMevery 200 ns, while the address is incremented. After 50,000,000 wordshave been written, “acquiring” mode ends.

Data Transmission. When “acquiring” mode has ended, the data isavailable to be read by the processor. The processor requests a 32k wordblock of data by setting bit 3 of the control register at address 0xf4,which clears when the block transmission starts. Before requesting atransmission, the processor may optionally specify the starting addressof the block by loading the “block start” register at address 0xf1. Ifthat register is not loaded, read out starts with block zero andcontinues in sequential block order through the entire memory. While theblock is being transmitted, the CPLD is in “transmitting” mode. In“transmitting” mode, each pair of data words is read out of the SDRAMand transmitted via the USB to the processor. The next pair of wordsfrom the SDRAM is read as soon as the previous pair of words has beentransmitted, so there is a continuous flow of data to the USB FIFO.

Normally the FIFO interface is only fast enough to read two words onevery other memory cycle, for a peak transmitted data rate of 5 MHz. Ifthe FIFO is not emptied promptly, its TXE# flag is negated and memoryreads are suspended until there is again room in the FIFO. Whentransmission of the 32,768 words in a block is complete, “transmitting”mode ends. Software may request blocks sequentially or in random order,and may ask for a block to be re-transmitted.

An example addressing scheme is depicted in the “USB Word Formats”diagram of FIGS. 16A-16C. USB Access To CPLD Registers. The USB FIFOinterface is 8 bits wide with no address information. Each commandcoming over the USB into the CPLD has an initial address byte containinga 3-bit register address and a read/write bit. The upper four bits of anaddress byte are all ones to assist in re-synchronizing in case sync islost; none of the upper bytes (at least) of write data will have thispattern. This allows for up to eight write commands and eight readrequests, providing sufficient capacity and room for expansion ifdesired.

For each write command, the address byte is followed by two data bytes,MSB first, although at some addresses some or all of the data will beignored. Since there is no longer a need for upper bit coding, the datais now aligned in right-justified natural binary form. For a readrequest, there are no data bytes following the address byte. Sending aread request causes the CPLD to place the requested data (two or fourbytes) in the USB FIFO where it may be retrieved by USB read commands. Aread request to the humidity sensor at address 0xfb returns four bytesin the FIFO; all other read requests (0xf8 for Threshold Register, 0xf9for Block Start, 0xfa for Barometric Sensor, 0xfc for Status Register)return two bytes in the FIFO.

A write to address 0xf0 (Threshold Register) stores the 11-bit value ina threshold register within the CPLD, used to set the incoming signalthreshold for starting data acquisition; this value may be read backwith a request to 0xf8. A write to address 0xf1 (Block Start MemoryAddress Register) is stored in the address counter, used to set thestarting memory address for a block data transmission; this value may beread back with a request to 0xf9. Use of 0xf2/0xfa for the barometricsensor and 0xf3/0xfb for the humidity sensor are detailed below.

The control and status registers are a pair of 16-bit registers locatedwithin the CPLD. The control register (from the processor to the frontend), written at address 0xf4, contains persistent bits to selectholster load resistance, select ADC range, and control a user LED. Italso contains self-clearing bits to enable acquisition, initiatetransmission of a block, or initiate test mode. The status register,read back at address 0xfc, contains readback bits for the persistentcontrol register bits, plus additional read-only status bits to reflectthe state of the main power converter, weapon inserted, acquisitionenabled, acquiring, and transmitting mode. When test mode is selected,the output word from the ADC registers is disabled, and the CPLDsubstitutes the lower 12 bits of the SDRAM address on the bidirectionaldata lines. This results in a predictable incrementing pattern beingwritten into the SDRAM during acquisition, in lieu of the ADC data. Theincrementing pattern resembles a sawtooth waveform, and can be usefulfor debugging the data acquisition and USB operations. The “test mode”bit is write-only, and clears itself at the start of the dataacquisition. “Weapon inserted” is detected with a mechanical switch inthe test fixture, connected to this board via 36 in FIGS. 12-12I. Itpresents a contact closure to digital ground. R13 converts that contactclosure to a 3.3-volt logic signal, which is filtered with R14, C28, and74VHC1G14 Schmitt trigger gate U7 to remove contact bounce. It isreadable as read-only bit 6 of the status register at address 0xfc.

Returning to FIGS. 12-12I, U11 is an FTDI FT232H USB 2.0 interface chip.USB Interface Chip. This chip bidirectionally interfaces a high-speedUSB port to the CPLD via a synchronous FIFO interface. The USB portconnects to either J3 (a USB micro-B connector) or J5 (a 10-pin 2 mmheader with MIO pinout). Two connectors are provided to allow use ofeither dual-USB-port connector on the processor board. D3 is a surgesuppressor across the USB data contacts, while ferrite bead FB3 filtersthe USB 5-volt supply for use by the front-end board. FB1 and FB2respectively filter the PHY and PLL supplies to the FT232H. Y1 is a 12MHz crystal configured as an oscillator with U11. An internal PLL(phase-locked loop) multiplies the frequency up to 480 MHz for USB use,and also provides a 60 MHz clock output for synchronous FIFO use. This60 MHz clock feeds the CPLD and both SDRAMs via a single seriestermination resistor and three equal length PC board clock traces. Whenreceiving data from the USB to the front-end board, U11 activates RXF#and provides the incoming data on the ADB[7 . . . 0] bus when the CPLDasserts OE# and RD#. To transmit data on the USB, the CPLD looks for theTXE# flag to be active and sends the data on the ADB[7 . . . 0] bus whenit asserts WR#.

10 MHz transmission is used. Logic within the CPLD sequences the FIFOcontrols, but the programmer should avoid trying to interleave USB readsand writes, or data and status reads, to attempt to avoid datascrambling. In general, transfers to or from control register, blockstart register, threshold register, environmental sensors, or statusregister should be done one at a time when a data block transmission isnot in progress. USB operations (except for writing the block startregister) may be performed during data acquisition.

Electrically Erasable Programmable Read-Only Memory. U12 is a serialEEPROM, required to use the synchronous FIFO mode of the FT232H. Itcontains configuration information for the FT232H. There is additionalspace in this EEPROM, which the program uses to store calibrationconstants for the four analog ranges. The EEPROM is programmed viasoftware in the processor at initial setup and at calibration time, andretains its data when power is removed.

Diagnostic LEDs. A set of seven diagnostic LEDs is provided to indicatethe operating mode, ADC range, weapon inserted, and the user LED, aswell as the status of RESET. The CPLD is globally reset by an externalGCLR# signal from a GPIO pin on the FT232H. This allows software toreset the front end board independent of the power-on reset. GCLR# ispulled down by R26 so this board is held in the reset state at power-upuntil the FT232H is configured.

FIGS. 13-13D depict a schematic diagram of a power circuit 708 utilizedin the hardware configuration of FIGS. 10A-10C. Onboard Power Supplies.FIGS. 13-13D depict the filtering, conversion, and distribution for thepower used on the board. The USB interface supplies a single digital +5volt supply to this board through MIO-pinout USB connector J5 and FB3,shown in FIG. 3. (For debugging purposes, a standard micro USBconnector, J3, is also provided.)

Onboard Power Filtering. +5VIN supplies maximum 120 mA directly to thedigital circuitry, mostly the FTDI chip. The +5VIN supply is also usedto generate a +3.3V digital supply at 400 mA maximum. +5VIN is filteredto provide the +5VA analog supply referred to AGND to the ADC andopamps, which has a maximum calculated output load of 80 mA. Thefiltered +5VIN is also used to generate the −5VA supply at 25 mAmaximum.

+3.3 V Converter. U14 is an LTC1627C buck regulator from LinearTechnology. It is configured as a synchronous buck converter usinginductor L4. The converter operates continuously (after USB enumeration)with a 350 kHz switching frequency. R44, R45, and C75 are the feedbacknetwork, chosen to provide an output voltage of +3.3 volts (referred todigital ground) to the CPLD, SDRAM, and the rest of the logic.

The result of the LT-Spice simulation for the LTC1627C showing theoutput voltage response to a 150-400-150 mA output load step is shown inFIG. 17A. The load add transient is 50 mV, the DC output shift underload is about 5 mV, the load dump transient is 50 mV, and ripple isabout 40 mV peak-to-peak.

Returning to FIGS. 13-13D, U13 is an LT1611C inverting switchingregulator from Linear Technology. It is configured as a coupled-inductorCuk converter using coupled inductor L3. (The symbol looks like atransformer, but the difference is that a transformer has energy flowingthrough from one winding to the other, while a coupled inductoralternately stores energy in the core using one winding, and releasesenergy using the other winding.) This circuit configuration provides lowswitching noise on both input and output, due to its continuous(triangle wave, non-pulsating) input and output current. The converteroperates continuously (after USB enumeration) with a 1.4 MHz internalswitching frequency while +5-volt power is supplied. R41, R42, and C69are the feedback network, chosen to provide an output voltage of −5volts referred to AGND. The output load on the −5VA supply is calculatedas 23 mA max.

The result of the LT-Spice simulation for the LT1611C showing the outputvoltage response to a 10-50-10 mA output load step is shown as FIG. 17B.The load add transient is 14 mV, the DC output shift under load is 3 mV,the load dump transient is 11 mV, and ripple is about 1 mV peak-to-peak.

Returning to FIGS. 13-13D, to reduce current draw on the USB supplyduring USB enumeration, both the +3.3V and −5VA converters power-up inthe off state, determined by PWREN#, a signal from the FT232H. Onceenumeration is done, PWREN# goes active-low and turns on both convertersby opening Q3 and Q4. Calculated load on the USB supply is maximum 530mA, just a bit over the allowed 500 mA, but since there is a captiveload on the processor and it is not operating over the full temperaturerange, operating slightly above the limit is acceptable. All threesupplies have green LEDs to indicate voltage present, and all threesupplies have Trans-Zorb zener transient suppressors to protect theloads from accidental arcing from the high-voltage pulse input.

FIGS. 14-14H depict a schematic diagram of a sensor circuit 710 utilizedin the hardware configuration of FIGS. 10A-10C. Sensors and InputConverter. FIGS. 14-14H depict two environmental sensors and abuck-boost input power converter.

Analog 3.3V Supply. L5 and C78 through C80 filter the digital +3.3-voltsupply and refer it to analog ground to produce a quiet +3.3VA at 1.2 mAfor use by the environmental sensors. D10 is a Trans-Zorb zenertransient suppressor to protect the load from accidental arcing from thehigh-voltage pulse input.

Barometer/Thermometer Chip. U15 is a Freescale MPL115A1 SPIbarometer/thermometer chip, allowing readings of the atmosphericpressure and temperature in the enclosure. C81 and C82 are bypasscapacitors, while R48 is a pull-up resistor for the open-collector DOUTline. The chip is always enabled. The chip has a bidirectional SPIinterface. The SPI signals are driven and received by logic within theCPLD. To issue a command to the barometer chip, the command is writtenas LSB data to address 0xf2. The first (high-order) data byte of the16-bit transfer is ignored, and the second (low-order) data bytecontains the command (with bit 0 set to 0, and bit 7 set to 0 for chipwrite or 1 for chip read). A chip write command is used to startconversion. Chip read commands are used for initially retrievingcompensation coefficients and for reading the pressure and temperatureresults of a conversion.

Upon a chip read command, the indicated byte is read from the chip intoa register in the CPLD. The serial data may take 5 microseconds totransfer. A read request to USB register address 0xfa is then used toget the upper byte of actual data into the USB FIFO. The chip's SPIinterface is 8 bits wide and all of the data to be read out of the chipis 16 bits wide, so this procedure must be repeated with the subsequentread command to get the lower byte. Note that all read data areleft-justified and padded with zeros on the least significant end. Table2 depicts a translation of the available commands:

TABLE 2 Available Command Translations 0x24 write Start conversion 0x80read Pressure result MSB 0x82 read Pressure result LSB 0x84 readTemperature result MSB 0x86 read Temperature result LSB 0x88 read a0coefficient MSB 0x8a read a0 coefficient LSB 0x8c read b1 coefficientMSB 0x8e read b1 coefficient LSB 0x90 read b2 coefficient MSB 0x92 readb2 coefficient LSB 0x94 read c12 coefficient MSB 0x96 read c12coefficient LSB

Once the chip powers up, read commands 0x88 through 0x96 are used toread the coefficients for compensation. (This data varies from chip tochip, but doesn't change on powering down or up. So where it's easier onsoftware to store the coefficients in the local EEPROM on the first“calibration” run rather than reading them from the chip on everypower-up, that may be done. Recalibration would need to be completed ifthe chip was replaced.) The coefficients are plugged into theappropriate equations as indicated in the data sheet. Then the only chipwrite command, 0x24 (CONVERT), is issued to start the conversion. Afterwaiting at least 3 milliseconds for the conversion to complete, theappropriate result data is read (again, one byte at a time). Once theuncompensated data is obtained, the compensated pressure can becalculated.

Hygrometer/Thermometer Chip. U16 is a Honeywell HIH6131-000-001 SPIhygrometer/thermometer chip, allowing readings of the humidity andtemperature in the enclosure. The temperature reading from this chip hasbetter resolution than the temperature reading from U15, althoughreading the chip is slower. C83 and C84 are bypass capacitors, while R50is a pull-up resistor for the SS# line. Red LED 11 indicates when aprogrammable on-chip humidity/temperature alarm has been activated. Thechip has a unidirectional SPI interface. Honeywell Technical Note00971-1-EN (July 2012) is useful in understanding SPI communicationswith this chip. The SPI signals are driven and received by logic withinthe CPLD.

This chip has one SPI command, a write command with data ignored.Writing that command requests both a new measurement and retrieves datafrom the previous measurement into a register in the CPLD. To issue acommand to the barometer chip, any value as data (0x0 suggested) iswritten to address 0xf3. (Data returned at this time may be ignored.)After a delay of at least 40 milliseconds to allow the conversion tocomplete, write again to address 0xf3 to fetch the data. Then wait forat least 70 more microseconds for the serial data to be retrieved, andissue a read request at address 0xfb to get the 32 bit word containingthe temperature, humidity, and two status bits (see the register map formore details). If the high-order two bits (status bits) are both zero,the data is fresh. If they are anything else, repeat the process untilfresh data is retrieved.

Universal DC Input Filter/Rectifier. The external coaxial wall-wartpower jack might be vulnerable to the use of an incorrect wall adapter.Rather than simply protecting against reverse or excessive voltage inputto the jack, the power input to the board is designed to allow operationfrom input voltages of either polarity from 10.8 to 26.4 volts. Reversepolarity voltage is rectified, and the incoming power is filtered andfed through a buck-boost switching power converter to raise or lower theinput voltage as required, and provide a regulated +12 volts at 2amperes output. The resulting +12 volt supply is used for the MIO board,fan, and load switching relays—all off-board loads. All of the powerused on this board comes from the +5 volt USB connection to the MIO.

Power coming in the coaxial jack is protected against transients by C85,PTC1, and D11. C85 snubs the fast rising edges of the transient,bidirectional transient suppressor D11 clamps any voltages over 26.7volts in either direction, and positive-temperature-coefficientthermistor PTC1 is designed to sharply increase in resistance upon athermal overload (caused by clamping of D11). The resultingsurge-protected voltage is fed through a filter composed of C86, L6, andC87, providing suppression of high-frequency noise. This is thenfull-wave rectified by Schottky diodes D12 through D15, and theresulting filtered, variable, positive voltage is fed to the buck-boostconverter. Note that despite the full-wave rectification, this circuitis not designed for use with a 60 Hz AC-output wall adapter. A frequencyand phase plot of the response of the entire input circuit is shown inFIG. 17C.

Buck-Boost Converter. A buck-boost converter can convert an incomingvariable voltage up or down as required. This particular topology isknown as a SEPIC (single-ended primary inductance converter). It isdistinguished by the twin inductor, coupling capacitor, andnon-inverting output. This is actually a variation of the inverting Cukconverter with the output connected upside down; the SEPIC has some butnot all of the efficiency and low-noise advantages of the Cuk converter.U17 is a Linear Technology LT3959EURE#PBF switching regulator chipdesigned specifically with SEPIC and Cuk converters in mind. Its switchis capable of handling a minimum of 6 amperes, which allows building aSEPIC converter with a small amount of boost capability that can deliver2 amperes at +12 volts. The chip runs at an 800 kHz switching frequency,selected by R57. The SEPIC circuit configuration has continuousnon-pulsating input current to reduce radiated noise on the input powercable. The chip is configured with a minimum startup voltage of 9.0 withoperation down to 8.0 using R51 and R55. This prevents attemptingoperation with 6-volt wall adapters which would run into the chip'scurrent limit. C76 selects a 27.5 millisecond soft-start time atpower-up to keep startup switching stresses low. C95, C97, C98, and R58are loop compensation components. R52 and R56 regulate the outputvoltage to just over +12 volts.

The result of the LT-Spice simulation for the L13959 showing the outputvoltage response to a 1-2-1 A output load step is shown in FIG. 17D. Thenominal output voltage is +12.1, the load add transient is 540 mV, theDC output shift under load is negligible, the load dump transient is 400mV, and ripple is about 35 mV peak-to-peak under full load. The outputstays within 5% during the load changes, and recovers in about 500microseconds.

Returning to FIGS. 14-14H, LED 12 indicates the status of the buck-boostconverter. When the chip's PGOOD# output is active-low, indicating thatthe output voltage is within regulation, emitter-follower Q7 turns onthe LED. PGOOD is also readable as bit 10 (bit 2 of the upper byte) ofthe status register at 0xfc; a ‘1’ indicates power is OK. Connectors J8and J9 supply regulated +12V and ground to the fan and MIO boardrespectively. +12V is also fed to J4 and the load relay drivers onschematic sheet 2. The operation of this converter is independent of therest of the front end board.

The apparatus and methods described herein may be used to testdischarges from stun devices to determine the actual operation of thedevices. It should be noted that each discharge from a stun device isnot necessarily identical, thus making routine testing desirable. FIG.18A depicts an “averaged waveform” from a commercially available stundevice. FIG. 18B depicts 50 waveforms from the identical stun device,that were combined to make the averaged waveform of FIG. 18A. Notably,FIG. 18B shows variants in the waveform for a plurality of discharges,including transients. Although the general waveform shape is the same,the variants present in each discharge may aid in determining thebiological effects of the stun device discharge on a human. FIG. 18Cdepicts a single discharge of the stun device of FIGS. 18A and 18B,depicting both voltage and the accumulating energy.

FIG. 19 depicts a method of testing an electric discharge stun device700. The testing method 700 may begin by first identifying the user ofthe test apparatus and/or stun device 702. This identification mayinclude one or more identification options. For example, the user mayscan a badge containing an RFID circuit 702 a. Alternatively oradditionally, a biometric sensor (fingerprint scanner, voice detectiondevice, eye scanner, etc.) may be utilized to identify the user. In abasic embodiment, a user may enter an identifying code or password,either through an external computer, or on the tester itself, to beginthe testing sequence. Thereafter (or initially, if identification of theuser is not desired), the stun device being tested may be identified tothe tester 704. This may include scanning an RFID tag 704 a located onthe device, scanning a bar code or other optical identification device,entering a device serial number into the external computer or the testeritself, or simply inserting the discharge end of a device into thetesting port . In operation 705, recordation begins. By beginningrecordation prior to discharge of the stun device, electrical leakage,prior to actual discharge, may be detected. Such leakage may beindicative of an operational problem. The resulting electrical dischargeis absorbed by the tester 706. Operation 706 may be repeated for anynumber of ports or test conditions. In one embodiment described herein,four separate ports are utilized. Recordation continues until noelectrical signal is recorded from the stun device, and recording isstopped, per operation 707.

Once the device has been discharged, the test device (or a computerconnected thereto) compares the discharge to known, stored information708. This comparison or analysis may serve a number of purposes. In oneinstance, the discharge may be compared to discharges of known stundevices from one or more manufacturers 708 a, this comparativeinformation being stored either locally, remotely, or both. By comparingthe discharge to the discharges of known stun devices, a previouslyunidentified stun device may be identified based on characteristics ofits discharge. If the device under test is of an unknown manufacture, oris a new model from a known manufacturer, the discharge may be analyzedto determine whether it matches a known device, or if it has a waveformsimilar to that already produced by a particular manufacturer.Alternatively, the discharge from a previously unknown or untesteddevice can be compared to known devices to determine if any dischargecharacteristics are shared. Knowledge of these discharge characteristicsand the body's response thereto can help determine if the device is safeto use. In a second instance, the discharge may be compared to aprevious discharge from the same device 708 b, thus allowing adetermination regarding the history and potential future performance(due to, for example, consistent waveform degradation) of the stundevice. Regardless of what information the discharge characteristics arecompared to, the information regarding the discharge may be stored in astorage medium 710, either locally 710 a on the tester, or remotely 710b on a computer or remote database. This stored information may be usedto create a repository of electrical discharge information for furtheraccess and study. In additional, information within the repository mayinclude specifications of known stun devices and analysis based on thephysical design of the device. In that regard, discharge characteristicsmay be predicted based on a comparison of specifications, as well.

FIG. 20 depicts a method of ensuring proper operation of an electricdischarge stun device 820, in accordance with one embodiment of thetechnology. As an initial operation, the device may be identified 822,either using an RFID reader 822 a or some other mechanism, as describedabove. Recording begins prior to discharge in operation 823. Next, auser activates the device against one or more ports of the tester, whichabsorbs the discharge 824, as described above. Once no furtherelectrical signal is received from the stun device, recordation stops825. In operation 826, the discharge of the device is compared to knowninformation, either from known stun devices 826 a or from the same stundevice 826 b. Again, issues attendant with the comparison and analysisare described above. Thereafter, the tester, or a computer associatedtherewith, analyzes the results of the comparison and makes adetermination as to whether the device is functioning properly, prior toany subsequent operation against a human target.

If the device discharges an appropriate waveform (e.g., corresponds tosome other waveform previously determined to be “safe” or withinmanufacturer's specifications), the tester may authorize subsequent useof the stun device on a target 828. This authorization may be made in anumber of ways. First, the tester may automatically enable or disablethe device 828 a, via a communication between the tester and theinternal circuitry of the stun device. This action may be made via thelead described with regard to FIG. 6A. Alternatively, the tester maysend out a wireless signal to enable or disable the stun device.Additionally, the tester may communicate to the user 828 b (either viaan audible or visible indicator) whether the stun device is performingproperly. In addition to an absolute indicator of proper performance,the testing device may calculate a confidence value for properperformance based on analysis of the waveform and comparisons to knownwaveforms. Additionally, authorization may not be required for everysubsequent discharge. The testing apparatus may authorize use of thestun device over a limited period of time, or until the stun device isnext used against a human target. Regardless of the authorizationoperation, the information regarding the discharge characteristics maybe stored 830, either locally 830 a or remotely 830 b, at least for thepurposes described above.

The two testing methods described above in FIGS. 19 and 20 enableanother function of the present technology. FIG. 21 depicts a method ofdetermining a biological response to an electric discharge from a stundevice 840, in accordance with one embodiment of the technology. Thefirst two operations are similar to those described above. A dischargeis first absorbed by the tester 842. Information from that discharge isnext compared to known information 844, either from the same stun device844 b, or from the repository of information regarding known stundevices 844 a, or even from theoretical information based on thephysical design of the stun device under test. Included in therepository are also known biological responses to known electricaldischarges from known stun devices 846 a. Based on this information, thetester can predict a likely biological response of a human target uponwhich the stun device is subsequently discharged 846, which may aid inan authorization operation 848, as described above with regard to FIG.20.

A variety of biological responses may be predicted based on theinformation obtained from the electrical discharge. Exemplary biologicalresponses may include those that affect all or a significant number ofmuscles of the body, for example, tetany, partial tetany, substantiallycomplete tetany, etc. Tetany and related biological responses aredescribed in U.S. Patent Application Publication No. 2007/0167241, theentire disclosure of which is hereby incorporated by reference herein inits entirety. In addition, it can be advantageous to determinebiological responses that may be considered undesirable or dangerous.Such biological responses may include organ damage, abnormal heartrhythms, epileptic seizures, localized cell death or damage (due to, forexample, burns), or complete incapacitation or death of the target.Additionally, information obtained from the electrical discharge maylead to a conclusion that no biological response or an ineffectivebiological response will be produced by the electrical discharge.

FIG. 22 depicts a method 900 of configuring a circuit in a stun devicetesting system in accordance with another embodiment of the presenttechnology. A testing device detects a condition indicative of a loss ofpower to a circuit contained therein in operation 902. This condition,also called an “Off” condition, may be detected due to a position of aswitch or a solenoid, or a loss of power to the circuit (due to, e.g.,unplugging of the tester). When in the Off condition, the circuit isautomatically configured to a default mode in operation 904. In thedefault mode, the circuit is automatically configured such a defaultresistor is disposed within the circuit, such that a discharge receivedfrom a stun device is routed through that default resistor. Thereafter,a discharge may be safely received by the tester circuit as in operation906. In an optional operation, the tester may issue a warning 908 towarn the user that the tester is not operational.

In operation 910, the tester detects a condition indicative of a receiptof power to the circuit. This condition is called the “On” condition.Once in the On condition, the tester may configure the circuit so as toobtain the required resistance required for a test, as in operation 912.In this case, the tester and corresponding circuit may only beconfigured for a particular type of test. In an alternative embodiment,the tester may first select a protocol from a library of protocols,operation 914, prior to setting selectively configuring the circuit soas to have a desired resistance. Thereafter, the tester is ready toreceive a discharge 916. Of course, the discharge recordation, analysisoperations, and result presentations, such as described in FIGS. 19-21may be performed at this time.

In the embodiments described above, the software may be configured torun on any computer or workstation such as a PC or PC-compatiblemachine, an Apple Macintosh, a Sun workstation, etc. In general, anycomputing device can be used, as long as it is able to perform thefunctions and capabilities described herein. The particular type ofcomputer or workstation is not central to the technology, nor is theconfiguration, location, or design of the database, which may beflat-file, relational, or object-oriented, and may include one or morephysical and/or logical components.

The servers may include a network interface continuously connected tothe network, and thus support numerous geographically dispersed usersand applications. In a typical implementation, the network interface andthe other internal components of the servers intercommunicate over amain bi-directional bus. The main sequence of instructions effectuatingthe functions of the technology and facilitating interaction amongclients, servers and a network, can reside on a mass-storage device(such as a hard disk or optical storage unit) as well as in a mainsystem memory during operation. Execution of these instructions andeffectuation of the functions of the technology is accomplished by acentral-processing unit (“CPU”).

A group of functional modules that control the operation of the CPU andeffectuate the operations of the technology as described above can belocated in system memory (on the server or on a separate machine, asdesired). An operating system directs the execution of low-level, basicsystem functions such as memory allocation, file management, andoperation of mass storage devices. At a higher level, a control block,implemented as a series of stored instructions, responds toclient-originated access requests by retrieving the user-specificprofile and applying the one or more rules as described above.

While there have been described herein what are to be consideredexemplary and preferred embodiments of the present technology, othermodifications of the technology will become apparent to those skilled inthe art from the teachings herein. The particular methods of operationand manufacture and configurations disclosed herein are exemplary innature and are not to be considered limiting. It is therefore desired tobe secured in the appended claims all such modifications as fall withinthe spirit and scope of the technology. Accordingly, what is desired tobe secured by Letters Patent is the technology as defined anddifferentiated in the following claims, and all equivalents.

What is claimed is:
 1. An apparatus comprising: a housing comprising aport for receiving a discharge end of an electrical discharge device;and an discharge-receiving circuit operatively connected to the port,the discharge-receiving circuit configured to receive a discharge fromthe electrical discharge device, wherein the discharge-receiving circuitcomprises: a plurality of resistors comprising a default resistor and atleast one supplemental resistor, wherein when in a first setting, thedischarge-receiving circuit is configured so as to pass the dischargeautomatically through at least the default resistor, and wherein when ina second setting, the discharge-receiving circuit is configurable so asto selectively pass the discharge through at least one of the pluralityof resistors.
 2. The apparatus of claim 1, wherein the at least onesupplemental resistor comprises a first supplemental resistor and asecond supplemental resistor.
 3. The apparatus of claim 2, wherein aresistance of the default resistor is higher than a resistance of atleast one of the first supplemental resistor and the second supplementalresistor.
 4. The apparatus of claim 1, further comprising a switch forselectively setting the discharge-receiving circuit to either of thefirst setting and the second setting.
 5. The apparatus of claim 1,wherein the discharge-receiving circuit is set to the first setting whenthe discharge-receiving circuit is unpowered.
 6. The apparatus of claim1, further comprising an environmental module for detecting at least oneof an ambient temperature, an ambient humidity, and a barometricpressure.
 7. The apparatus of claim 1, further comprising an air intakefan for drawing ambient air into the housing, and wherein theenvironmental module detects at least one of the ambient temperature andthe ambient humidity, and wherein the environmental module is disposeddownstream of the air intake fan.
 8. The apparatus of claim 1, whereinthe discharge-receiving circuit further comprises an analysis module. 9.A method of configuring a circuit, the method comprising: detecting acondition indicative of a loss of power to the circuit; configuring thecircuit such that an electrical discharge through the circuit is routedthrough at least one of a plurality of resistors, wherein the electricaldischarge is received from a device located external to the circuit. 10.The method of claim 9, further comprising receiving the electricaldischarge from the external device.
 11. The method of claim 9, furthercomprising: detecting a condition indicative of a receipt of power tothe circuit; and selectively configuring the circuit so as to route thedischarge through at least one of the plurality of resistors.
 12. Themethod of claim 11, further comprising: selecting a protocol; andselectively configuring the circuit based at least in part on theselected protocol.
 13. The method of claim 9, wherein the condition isbased at least in part on the position of a switch in the circuit. 14.The method of claim 9, wherein the condition is based at least in parton an absence of supply power to the circuit.
 15. The method of claim 9,wherein configuring the circuit comprises at least one of opening orclosing a solenoid.
 16. The method of claim 9, wherein the circuit isdisposed within a testing device.